Add binary & ascii STLs and OBJs
Added matlab code samples.

All of these code samples currently are mis-identified in my repositories. I'm
donating them to the cause.
Removed copyrighted file.
Add Verilog/SystemVerilog filename extensions

Most Verilog files use the *.vh extension for header files.

Since the IEEE 1800-2009 SystemVerilog standard, it is common for
hardware and verification files written using the newer language
constructs to use the *.sv extension for design elements, and *.svh for
headers.
Merge pull request #367 from moorepants/matlab-samples

Added matlab code samples.
Regenerate samples.json
Merge pull request #368 from cjdrake/master

Add Verilog (.vh) and SystemVerilog (.sv, .svh) filename extensions
Merge pull request #360 from skalnik/add-solid-support

Add Blob#solid? helper
Alphabetize verilog extension list
Add .bash and .tmux as alternate shell extensions
Merge pull request #372 from github/more-shell-extensions

Add .bash and .tmux as alternate shell extensions