Add definitions for the PPC a2q core marked as having QPX available

This is the first commit of a large series which will add support for the
QPX vector instruction set to the PowerPC backend. This instruction set is
used on the IBM Blue Gene/Q supercomputers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
...in light of recent activity related to llvm.memcpy flags. I want to
prevent an llvm developer from mistakenly thinking that just because the
intrinsic has volatile flags that volatile operations can be converted
to or folded into them.

Platforms may rely on volatile loads and stores of natively supported
data width to be executed as single instruction. When compiling
C, this expectation likely holds for l-values of volatile primitive
types with native hardware support, but not necessarily for aggregate
types. The frontend upholds these expectations, which are not
specified in the IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173974 91177308-0d34-0410-b5e6-96231b3b80d8
Remove redundant code.

It was creating a new AttrBuilder when we could just fill in the AttrBuilder
we're building.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173975 91177308-0d34-0410-b5e6-96231b3b80d8