aarch64: Implement simd scalar faddp instruction.

Implement single and double-precision scalar faddp variants, and skeleton
of decoding parts for similar fminp/fmaxp/etc. insns.
aarch64: Implement simd vector FMUL.

Implement FMUL. FMULX remains unimplemented.
aarch64: Implement simd vector FMLA/FMLS.

Also fix FMUL support to load the right size of element.
aarch64: fix FDIV operand size.

Operands were being loaded as bytes/halfwords instead of words/doublewords.
aarch64: simd movi floating-point immediate variant fix.

Fix decoding of single and double-precision floating point immediates
for simd movi instructions.
aarch64: Fix clobbering of input register in tbl/tbx helper.

When the output register overlaps with the table-lookup registers,
the input could be clobbered before the operation completes (in the Q
register case). Also "is_tbl" variable in the same helper function is
renamed to "is_tbx".
aarch64: Fix ZIP2 instruction.

The second half of D-sized vectors was being located incorrectly.
aarch64: Implement simd element DUP.
Merge pull request #2 from jtb20/aarch64-1.6

cool, thank you