fs/dyn_sync_cntrl: dynamic sync control

The dynamic sync control interface uses Android kernel's unique early
suspend / lat resume interface.

While screen is on, file sync is disabled
when screen is off, a file sync is called to flush all outstanding writes
and restore file sync operation as normal.

Signed-off-by: Paul Reioux <reioux@gmail.com>
Increase readahead value to 1MB.
thermal: tsens: Leave sensors enabled on TSENS init.

This change allows kernel thermal mitigation to read sensors
that are not the main sensor (TSENS0) even after the driver probe
occurs.

Change-Id: I84927592be60ba5795c641a4ff7c467d39acf75b
Signed-off-by: Eugene Seah <eseah@codeaurora.org>
thermal: tsens8960: Increase the polling rate

Change the polling rate at which the sensors temperature
is read from 1 second to .25 seconds. On faster parts
there is a need to poll the temperature at a higher
frequency to improve reporting temperature changes.

Change-Id: I10049707c3e55316597fff72fbd00246cd29bed3
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
gpu: ion: Use writecombine for uncached mappings

When we map ion buffers as uncached we want to map them as
uncached but still be able to use buffering of transactions
since turning off buffering has a severe performance impact.

Change-Id: I5a09ac34bd3ce3f001d10d9efd71d140f632564d
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
gpu: ion: Request highmem pages for IOMMU heap

When allocating pages for IOMMU heap it is advantageous
to try to allocate pages from highmem in addition to
lowmem since clients using the IOMMU heap can use
either highmem or lowmem.

CRs-fixed: 430457
Change-Id: Ifc794fc344c67dd53d8f7cebf86536ab9d44ed6c
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
gpu: ion: replace __GFP_ZERO with manual zero'ing

As a performance optimization, omit the __GFP_ZERO flag when
allocating individual pages and, instead, zero out all of the pages in
one fell swoop.

Change-Id: Ieb9a895d8792727a8a40b1e27cb1bbeae098f581
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
gpu: ion: allocate huge pages in iommu heap

As a performance optimization, use higher-order page allocations if
possible. This can reduce TLB misses and the total number of page
structures.

CRs-Fixed: 449035
Change-Id: I6b76ec69599a100fd7209161c4286284ae347be0
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Use pgprot_writecombine in ion_system_heap_map_kernel for optimization.
msm: kgsl: Enable "big page" memory allocations

Allow users to specify "big page" mode when allocating GPU
memory. This will attempt to allocate contigious units of 64k
bytes per instead of the usual PAGE_SIZE units.  If the allocation
fails, then automatically fall back to allocate the rest of the
region with 4K pages. This means that potentially any allocation
could be comprised of a mixture of 64k chunks and 4k chunks.

Change-Id: Ic0dedbadcf1f4b30a106f430dd2d87781ea54829
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: acpuclock-krait: NULL terminate L2 table for find_cur_l2_level()

find_cur_l2_level() assumes that the L2 table is NULL terminated
when it has never been terminated. Therefore, if the rate that is
read from the hardware during boot is not found in the table we
will run off the end of the table and read potential junk values.
NULL terminate all the L2 tables so that the loop in
find_cur_l2_level() is guaranteed to terminate.

Change-Id: Ia5d0213000b44def35e388fd3cadf0293344257b
Reported-by: Laura Abbot <lauraa@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: acpuclock-krait: Keep the secondary MUX input fixed

With use of the QSB clock source recently eliminated, only one
input of the secondary clock MUX is used on any target. Since
there is overhead involved reprogramming this MUX when changing
the CPU and L2 frequencies, change the code to just program the
MUX at boot.  Most noticeably, this removes a 1us delay from
every CPU and L2 frequency switch.

Change-Id: I5cd8c981f1be49be7dbba1310d84df439e8be83b
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: acpuclock-8064: Lower VDD_DIG voltage vote for L2 at 384MHz

New characterization data shows that vdd_dig voltage for L2@384MHz
can be lowered to 0.95v. Update the data in this patch.

Change-Id: Ibdb8568eca4d4ed602c5a5fee2f433a098dfbdcd
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
msm: acpuclock-8064: Add support for 8064v1.1 FASTER PVS bin

Add updated PVS data.

Change-Id: I011241d3ea3943673a888cd0aeca925440500ff2
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: dcvs: change tz buffer to 32KB

Only around 32K of buffer is required for normal operation.
Request the scm buffer of 32kb from the contiguous area.

Change-Id: If79471c6e0cfe80b1796a14d83ea10eb6b919e40
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

*revised patch to apply to Mako
msm: cpuidle: Don't disable irqs again

cpu_idle() disables irqs before calling down into the cpuidle
driver via cpuidle_idle_call(). Disabling irqs again in
msm_cpuidle_enter() is wasteful and unnecessary. It also inhibits
our ability to determine the largest irq latency when the cpu
idles for extended periods of time because the irqsoff trace is
reenabled when the irqs are disabled in msm_cpuidle_enter().

Note that we still reenable irqs before returning, as is required
by the ARM idle loop.

Change-Id: I925478d8fef88ab490959622bc68303f59cc6e79
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: dma: Moving queue_work() function within spinlock

Currently we are adding a dma command to the staged list with in a
spinlock and then adding to workqueue using queue_work after unlocking
the spinlock. With this there is chance of executing DMA commands in out
of order in below concurrency case.

Tread1                                Thread2
__msm_dmov_enqueue_cmd_ext
   spin_lock_irqsave(..)
   list_add_tail(..)
   spin_unlock_irqrestore(..)
       --PREEMPT--
                                      __msm_dmov_enqueue_cmd_ext
                                         spin_lock_irqsave(..)
                                         list_add_tail(..)
                                         spin_unlock_irqrestore(..)
                                         queue_work()
                                         ..
   queue_work()
So adding queue_work with in spin_lock will make sure that the
work added in the work_queue is processed in the same order as they
are added in staged_commands.

CRs-Fixed: 423190
Change-Id: I2ffd1327fb5f0cd1f06db7de9c026d1c4997fe4d
Acked-by: Gopi Krishna Nedanuri <gnedanur@qti.qualcomm.com>
Signed-off-by: Utsab Bose <ubose@codeaurora.org>
EHCI: HSIC: Handle wakeup interrupt properly during probe

During HSIC probe driver registers the level triggered interrupt
on wakeup gpio. Wakeup irq line is disabled based on the return
status of interrupt registration. There is a possibility that
wakeup gpio is already pulled high after registering the interrupt
which can cause wakeup interrupts to be fired on continuously
without getting chance to disable the irq line. Hence do not
enable wake up interrupt on request irq.

CRs-Fixed: 394540
Change-Id: I3175cd8710f1d982c33a5392cc49106ee66d0aa6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
EHCI: HSIC: Add support to vote for SVS digital voltage

HSIC HW can operate at SVS digital voltage when it is active.
Currently HSIC is voting for 120Mhz SFAB and 64Mhz DFAB clock
frequencies. Clock frequencies are directly proportional to SVS
voltage. If DFAB is running at 64Mhz or SFAB is running at 120Mhz
or higher SVS is not possible even though HSIC votes for it. Hence
do not vote for SFAB clock frequency and only vote for 32Mhz for
DFAB in order to allow SVS to happen. Voting for SVS voltage reduces
current consumption by 3mA in HSDPA network.

Change-Id: I8a6844efbbe90a8ea118be8450f8210717c2641b
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Vote for SVS voltage of 32Mhz on mako.