target-arm: aarch64: add support for 2-src shift reg insns

this adds 2-src variable shift register instructions
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 45/60