Hexagon - Add peephole optimizations for zero extends.

	* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
Replaced usages of size_type with size_t to be more consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180947 91177308-0d34-0410-b5e6-96231b3b80d8
We don't want FP elimination when doing an Apple-style build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180949 91177308-0d34-0410-b5e6-96231b3b80d8
[GV] Remove dead code which is really difficult to decipher.

Actually it took me couple of hours trying to make sense of them and
only to find they are dead code.  I guess the original author used
"allSingleSucc" to indicate if there are any critial edge emanating
from some blocks, and tried to perform code motion (actually speculation)
in the presence of these critical edges; but later on he/she changed mind
and decided to perform edge-splitting first.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180951 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Prettier asmPrint of Alu

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Improve asmPrint of ALU clause

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add a test to check that use_kill is emitted

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180958 91177308-0d34-0410-b5e6-96231b3b80d8
R600: If previous bundle is dot4, PV valid chan is always X

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Signed literals are 64bits wide

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960 91177308-0d34-0410-b5e6-96231b3b80d8
reverting r180953

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
Remove redundant flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180967 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Handle reading, writing or copying of ccond field of DSP control
register.

- Define pseudo instructions which store or load ccond field of the DSP
  control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
In MC asm parsing, account for the possibility of whitespace within
the "identifier" parsed by the frontend callback by skipping forward
until we've consumed a token that ends at the point dictated by the
callback.

In addition, inform the callback when it's parsing an unevaluated
operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one
(e.g. mov eax, [A::x]).

This commit depends on a clang commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180978 91177308-0d34-0410-b5e6-96231b3b80d8
Fix missing include in Hexagon code for Release+Asserts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Remove "Commutative" from property list of non-commutative intrinsics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180988 91177308-0d34-0410-b5e6-96231b3b80d8
Correctly testing for AVX support in x86 based off code from Hosts.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180991 91177308-0d34-0410-b5e6-96231b3b80d8
Unbreaking the non-x86 build bots by protecting the AVX test code properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180992 91177308-0d34-0410-b5e6-96231b3b80d8
Added pocl and TCE blurbs to the ReleaseNotes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181001 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Add target description for btver2; make autodetection logic aware of AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005 91177308-0d34-0410-b5e6-96231b3b80d8