add cache header and memory interface
corrected some headers
access time and hit ratio accomodated
cache initialization code
cache initialization code #8
Merge branch 'memory' of https://github.com/ah450/RiSC-16-Simulator into memory
added testing #8
all tests passed #8
add code for single level + tests #9
multileve cache and test #10
main memory #11 and tests
finished main memory #11
Merge branch 'memory'