verilog and constraints files to use with vivado
Added in missing AXI wid signals
git ignore *.bo files (bluespec compiler output)
updated copyright notice
update to work with vivado
remove generated file
fix the generated Makefile
support HDMI in vivado builds
Added BlueScope alternative to chipscope ila
ignore .so and .ba files
Use PS7 GP%d for 32-bit AXI masters and HP%d for 64-bit AXI masters
had input and output wires swapped on I2C scl and sda IOBUFs
separate project creation script from projbect build tcl script
ps7 SP%d and HP%d use 6-bit transaction ids
xadc and bus width cleanup
updated README.md with note about creating .bit/.bin files with Vivado
added a comment to the .tcl file about creating a .bin file
create both .bit and .bin files
remove XADC_gpio, fix HDMI and LED pin bindings for zc702
added script to byte-reverse bit.bin output file from vivado