Added read_ctl

Simple state machine to latch read operations on the wishbone bus.
Set uart_tx rdy based on state
Add read fifo and UART

* Added a read_ctl instansiation to put wishbone reads into the FIFO
* Added a UART to transmit the wishbone reads via UART
* Synthesized a hardware FIFO using smartgen
Use clk_o, rst_o nomenclature in ddk_core
Remove cruft
Add UART output to fifo
Use assigns for Synopsys
Updated hardware FIFO

* Use only 2 SRAM blocks
Add read_fifo to ddk_core