Update sample code for date/time.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14614 6f19259b-4bc3-4df7-8a09-765794883524
Add Memory fence for ARM Architecture (32 and 64 bit)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14615 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg/ArmLib: Change comment to match code for setting of V bit in SCTLR register.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14616 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg/CpuDxe: Fixed calculation of the Page Table Index (Level 2 Descriptor)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14617 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg/ArmDmaLib: Fixed the calculation of the Base Address of the Buffer

The former calculation 'ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB)' did
not return the lowest aligned address.

Example:
*DeviceAddress = 0xB000C001;
*DeviceAddress - BASE_4KB - 1 = 0xB000B000;
Aligned value = 0xB000B000 + ((0x1000 - 0xB000B000)) & 0xFFF) = 0xB000B000
... while we where expected 0xB000C000.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14618 6f19259b-4bc3-4df7-8a09-765794883524
Merge branch 'master' of https://github.com/tianocore/edk2