target-arm: A64: provide skeleton for a64 insn decoding

provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) C3

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: A64: expand decoding skeleton for system ins

this change splits the system instructions into
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL,
sync instructions, which include CLREX, DSB, DMB, ISB,
msr_i, which move immediate to processor state field,
sys, which include all SYS and SYSL instructions,
msr, which move from a gp register to a system register,
mrs, which move from a system register to a gp register.

This is only the skeleton, not the actual implementation
for all the instructions above.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
target-arm: A64: add set_pc cpu method

When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 06/60
target-arm: A64: add support for B and BL insns

This adds handling for the B and BL instructions,
which require to be able to access a register and generate jumps.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: renamed functions,
          protected new A64 tcg constants in DisasContext with
          #ifdef TARGET_AARCH64,
          adapted to new decoder layout]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 09/60
target-arm: A64: add support for BR, BLR and RET insns

Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: reimplemented on top of new decoder structure]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 10/60
target-arm: A64: add support for logical (shifted register)

this adds support for the instructions described in:
C3.5.10 Logical (shifted register)

Support includes a reworking of flags, and a way to read the
registers in copy mode that also zero extends on 32bit access.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 14/60
target-arm: A64: add support for ADR and ADRP

this adds support for the instructions described in:
C3.4.6 PC-rel. addressing (ADR and ADRP).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 26/60
target-arm: A64: add preliminary support for MSR/MRS

this is very very limited: we only support
setting and getting NZCV (C4.3.10),
getting CTR_EL0 (D8.2.21) with a hardcoded value,
getting DCZID_EL0 (D8.2.23) with a hardcoded value,
getting and setting TPIDR_EL0 (D8.2.87).

Eventually this could be rewritten on top of arm_cp_regs API
with some refactoring necessary (main issue: ARM_CP_64BIT)

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure, put common code
          between MSR/MRS in a separate function, add NZCV,
          add support for writing to TPIDR_EL0,
          fixed high bit of CTR_EL0]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 35/60, 36/60
target-arm: A64: MRS/MSR for FPCR access

Add FPCR to the set of registers handled by MRS/MSR;
implemented via calls to helper functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: A64: add support for conditional branches

This patch adds emulation for the conditional branch (b.cond) instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure,
          reused arm infrastructure for checking the flags]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 34/60
target-arm: A64: add support for conditional select

this patch adds support for "C3.5.6 Conditional select",
which means CSEL, CSINC, CSINV, CSNEG.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 43/60
target-arm: A64: add support for 'test and branch' imm

this patch adds emulation for the test and branch insns,
TBZ and TBNZ.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted for new decoder,
          always compare with 0, remove a TCG temporary]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 40/60
target-arm: A64: add support for compare and branch imm

this patch adds emulation for the compare and branch insns,
CBZ and CBNZ.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder,
          compare with immediate 0, use read_cpu_reg to get
          the 0 extension on (!sf)]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 33/60
target-arm: A64: add support for EXTR

This patch adds emulation support for the EXTR instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted for new decoder, removed a few temporaries,
          fixed the 32bit bug, added checks for more
          unallocated cases]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 30/60
target-arm: A64: add support for 2-src data processing and DIV

this patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder adding the 2-src decoding level,
          always zero-extend result in 32bit mode]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 44/60
target-arm: A64: add support for 2-src shift reg insns

this adds 2-src variable shift register instructions
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 45/60
target-arm: A64: add support for 1-src data processing and CLZ

this patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ(count leading zeroes).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, simpler path for 64bit form,
          reuse 32bit helper for 32bit form]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 47/60
target-arm: A64: add support for 1-src RBIT insn

this adds support for the C5.6.147 RBIT instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, use bswap64,
          make RBIT part standalone from the rest of the patch,
          will handle REV in a separate patch]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 46/60
target-arm: A64: add support for 1-src REV insns

this adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 46/60
target-arm: A64: add support for bitfield insns

this patch supports C3.4.2 Bitfield instructions
SBFM, BFM, UBFM.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 31/60