[mips] Add instruction selection pattern for (seteq $LHS, 0).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181459 91177308-0d34-0410-b5e6-96231b3b80d8
Add line tracking support to FormattedStream 
- previously formatted_raw_ostream tracked columns, now it tracks lines too
- used by (upcoming) DebugIR pass to know the line number to connect to each IR
  instruction



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181463 91177308-0d34-0410-b5e6-96231b3b80d8
Pull up AssemblyWriter interface into header to allow subclassing
- made all functions virtual so that subclasses can specialize them
- add printInstructionLine so that subclasses can choose whether or not to
  print the newline character (without having to implement printBasicBlock()
- added a second constructor to AssemblyWriter that does not require a
  SlotTracker, as required in order to keep the SlotTracker helper class outside
  AsmWriter.h and buried in the implementation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181466 91177308-0d34-0410-b5e6-96231b3b80d8
Add DebugIR pass -- emits IR file and replace source lines with IR lines in MD
- requires existing debug information to be present
- fixes up file name and line number information in metadata
- emits a "<orig_filename>-debug.ll" succinct IR file (without !dbg metadata
  or debug intrinsics) that can be read by a debugger
- initialize pass in opt tool to enable the "-debug-ir" flag
- lit tests to follow



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181467 91177308-0d34-0410-b5e6-96231b3b80d8
DebugIR tests -- lit tests for the line number transform
- simple one-function case
- function-calling case
- external function calling case
- exception throwing case
- vector case

Note: these tests are somewhat coupled to the current format of debug metadata.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181469 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure debug info contains linkage names (DW_AT_MIPS_linkage_name)
for constructors and destructors since the original declaration given
by the AT_specification both won't and can't.

Patch by Yacine Belkadi, I've cleaned up the testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181471 91177308-0d34-0410-b5e6-96231b3b80d8
Revert 181475 as the DebugIR tests are breaking (automake) buildbots that re-use build dirs
- the temporaries "-debug.ll" files generated by DebugIR pass are considered tests, even though they are not



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181476 91177308-0d34-0410-b5e6-96231b3b80d8
Use correct parameter names in comments [-Wdocumentation]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181478 91177308-0d34-0410-b5e6-96231b3b80d8
LoopVectorizer: Don't assert on the absence of induction variables

A computable loop exit count does not imply the presence of an induction
variable. Scalar evolution can return a value for an infinite loop.

Fixes PR15926.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181495 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Make sure debug info contains linkage names (DW_AT_MIPS_linkage_name)"
temporarily while investigating gdb.cp/templates.exp.

This reverts commit r181471.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181496 91177308-0d34-0410-b5e6-96231b3b80d8
Change getRelocationAdditionalInfo to be ELF only.

It was only implemented for ELF where it collected the Addend, so this
patch also renames it to getRelocationAddend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181502 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit.

Add one of my contributions to CREDITS.TXT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181508 91177308-0d34-0410-b5e6-96231b3b80d8
Introduce convenience typedefs for the 4 ELF object types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181509 91177308-0d34-0410-b5e6-96231b3b80d8
libDebugInfo depends on libObject nowadays.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181510 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid runtime type checks.

In most cases the relocation type implies the object word size and
endianness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181515 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Don't just copy known bits from the first operand of an srem.

That's obviously wrong. Conservatively restrict it to the sign bit, which
matches the original intention of this analysis. Fixes PR15940.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181518 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Fix handling of functions where only the LR is spilled.

Previously we only checked if the LR required saving if the frame size was
non zero. However because the caller reserves 1 word for the callee to use
that doesn't count towards our frame size it is possible for the LR to need
saving and for the frame size to be 0.

We didn't hit when the LR needed saving because of a function calls because
the 1 word of stack we must allocate for our callee means the frame size
is always non zero in this case. However we can hit this case if the LR is
clobbered in inline asm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181520 91177308-0d34-0410-b5e6-96231b3b80d8
Don't replace an alias in llvm.used with its target.

When we replace an internal alias with its target, be careful not to
replace the entry in llvm.used (and llvm.compiler_used).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181524 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify the code a bit.

The compact unwind registers were defined in two different
places. It's better just to place them in the function that uses them
and specify that this is a 64-bit or 32-bit machine.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181529 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Use relation map for getMatchingCondBranchOpcode() and 
getInvertedPredicatedOpcode() functions instead of switch cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181530 91177308-0d34-0410-b5e6-96231b3b80d8