Jack's fix for sync period constant value.
Support for design information generation at build
Merge branch 'master' of github.com:ska-sa/mlib_devel
Allow register retiming to ease logic requirements

Various delays in the delay_slr, reorder and fft_stage_n blocks
implemented in behavioural HDL to ease logic requirements.
Restore sys_clk2x on ROACH2

Commit bd4df16 mucked around with the sys_clk MMCM config and wiring.  It left
the sys_clk2x signal driven by a BUFG that was driven by an undriven signal
(sys_clk2x_mmcm).  Surprisingly, the tools were happy to go along with this and
ended up driving that BUFG with GLOBAL_LOGIC0.  This meant that sys_clk2x was a
constant logic '0' instead of a 200 MHz clock.  Anything clocked by sys_clk2x,
such as the qdr_controller's div_clk input, would never be clocked.  Doh!

This restores sys_clk2x by making it a copy of the clk_200 signal that was
added in commit bd4df16.

It would be a good idea to go through and review/reconcile all of the clocks
being generated.  For example, it appears that sys_clk2x{90,180,270} have not
been driven by real clocks since commit 1c2035e.  Fortunately, it appears that
nothing uses these phases of sys_clk2x90, but that begs the question of why
they exist at all then.
Merge branch 'master' of http://astro.berkeley.edu/~davidm/mlib_devel
register retiming for pfb_fir_generic components

Saves a fair amount of registers and luts