General:
- Rearranged verilog code structure
- Removed unnecessary files

ps_pl_interface.v:
- Fixed sprodically missed interrupt bug by stretching the pulse width of the interrupt signal
- Added FIFO to in AXI4-Stream data path to compensate for asymmetric AXI ACP read/write speed. The AXI ACP read speed is faster than the write speed and the FIFO provides prevents dropped samples due to overflow.