(Binary Analysis) Moved byte order stuff to its own namespace

Stuff related to byte order was originally part of the SgAsmGenericFileFormat
class, which made it difficult to use in parts of ROSE that aren't
related to parsing a binary container for holding an executable, library,
object file, or coredump.

So I moved all this stuff into a ByteOrder namespace. Other than the
name space, only one name changed: the SgAsmGenericFileFormat::ByteOrder
enum is renamed to ByteOrder::Endianness.
(Binary Analysis) Memory maps have an intrinsic byte order
(Binary Analysis) PartialSymbolicSemantics can read from MemoryMap

A memory map can be given to PartialSymbolicSemantics as in the
old API. The memory map supplies values for read-only memory to
use when the readMemory() Risc operation encounters a memory address
it doesn't yet know about.
(Binary Analysis) A couple more changes related to moving byte order facilities
(Binary Analysis) Cell-list memory can return its list of cells
(Binary Analysis) Documentation
(Binary Analysis) Added RegisterDescriptor::is_valid()

This is the formal way to determine whether a register descriptor
actually refers to a register or was default constructed.
(Binary Analysis) X86 dispatcher throws exception if insn is not 32-bit

This is necessary because we sometimes call instruction semantics with
64-bit code even though 64-bit code isn't officially supported yet. Some
of the x86 instruction handlers fail assertions when called for 64-bit
code, and we want to avoid that.
(Binary Analysis) Geneneralized memory read/write for binary semantics

* Removed x86-specific data types from readMemory and writeMemory
  RISC operations.  The segment register information is passed into
  these operations via a RegisterDescriptor rather than an X86SegmentRegister
  enum.

* Generalized x86 dispatcher's read/write memory operations and moved
  them into BaseSemantics::Dispatcher in preparation for adding
  PowerPC semantics.
(Binary Analysis) Updated test answers for x86 LEA instruction

The effectiveAddress calculation was generalized and moved from
x86-specific code to BaseSemantics::Dispatcher. As a result,
the result width is computed slightly differently, and thus the
symbolic expressions are different.  Namely, instead of:

  A = (extract 0 32 (unsignedMultiply (signExtend 32 X), signExtend(32, Y)))

we have

      { (unsignedMultiply X Y)                 if X.nbits() + Y.nbits() == 32
  A = { (extract 0 32 (unsignedMultiply X Y))  if X.nbits() + Y.nbits() > 32
      { (signExtend 32 (unsignedMultiply X Y)) if X.nbits() + Y.nbits() < 32
(Binary Analysis) Partitioner jump table discovery uses semantics API2
(Binary Analysis) Generalized binary semantics interrupt mechanism

Changed the RiscOperators::interrupt() interface so that it can be
used for architectures other than x86.

Removed the x86-specific sysenter() RISC operator.  The x86 SYSENTER
instruction uses the generic interrupt() RISC operation.
(Binary Analysis) Added PowerPC instruction semantics to API2

This implementation in the ROSE library is based on two different
implementations in the SemanticSignatureVectors and assemblyToSourceAst
projects.  The implementations in those projects should be considered
deprecated -- using them would require more cut-n-pasted code anyway
since they're not part of the ROSE library.