bus/asmibus: use implicit finalization
README: update
fhdl/tracer: remove leading underscores from names
fhdl/tracer: recognize LOAD_DEREF opcode
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
bank: automatic register naming
fhdl/specials/Memory: automatic name#
fhdl/verilog: implicit get_fragment
examples/basic: use new APIs
vpi: make it work by default on Arch
sim/generic: support implicit get_fragment
examples/pytholite: use new APIs
Add support for negative slice indices

In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].

Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
	reg.eq(Cat(Replicate(0, n), reg[-n:])

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Allow SimActors to produce/consume a constant stream of tokens

Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.

The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
bank/description: modify reg/mem in-place
bank/csrgen/BankArray: create banks in sorted order
flow/actor/filter_endpoints: deterministic order
Make ClockDomains part of fragments
Local clock domain example
sim: compatibility with new ClockDomain API