mips: implement Iop_8Uto64 in iselInt64Expr

Iop_8Uto64 was missing in iselInt64Expr.
The change should resolve Bugzilla #319505.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2729 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add support for
(T1) STRBT reg+#imm8
(T1) STRHT reg+#imm8
(T1) LDRBT reg+#imm8
(T1) LDRSBT reg+#imm8
(T1) PLI reg+#imm12
(T2) PLI reg-#imm8
(T3) PLI PC+/-#imm12

Fixes: 319858 319932 320083 321693 321148

(Vasily, w.golubev@mail.ru)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2730 8f6e269a-dfd6-0310-a8e1-e2731360e62c

Implement the following instructions, in both ARM and Thumb
encodings:
  SSAX SXTAB16 SHASX SHSAX SHSUB16 SHSUB8
  UASX USAX UQADD16 UQASX UQSAX UHASX UHSAX REVSH

Fixes
  321363 321364 321466 321467 321468 321619 321704
  321620 321621 321692 321694 321696 321697 321703

(Vasily, w.golubev@mail.ru)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2731 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips32: Add support for mips32 DSP instruction set.

Add support for mips32 DSP and DSP revision 2 ASE.
More details about the mips32 DSP(r2) ASE:
http://www.mips.com/media/files/MD00566-2B-MIPSDSP-QRC-01.00.pdf
Applied patch provided by Maja Gagic <maja.gagic@rt-rk.com>


git-svn-id: svn://svn.valgrind.org/vex/trunk@2732 8f6e269a-dfd6-0310-a8e1-e2731360e62c
s390: New machine model: zBC12


git-svn-id: svn://svn.valgrind.org/vex/trunk@2733 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips32: Correctly model SHLL_S.PH on MIPS32.

Fix problem with IRTemp size when modeling SHLL_S.PH on MIPS32.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2734 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Rename ppc_cache_line_szB to indicate that this is the size
of the instruction cache.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2735 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Do not use the 0b notation as older GCC's do not accept it.
Fixes BZ 322851 and also unbreaks the OS X nightly build (hopefully).
Patch by Thomas Rast (trast@student.ethz.ch).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2736 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Update Makefile-gcc to include additional files that were added in r2702.
Fixes BZ 319494.
Patch by Stephen McCamant (smcc@CS.Berkeley.EDU).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2737 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add a spec rule for SUBQ/NLE.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2738 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add infrastructural support (IR, VEX) to allow returns of 128-
and 256-bit values from dirty helper functions, in a way which is
independent of the target ABIs and of compilers generating
correct struct return code.

Is a prereq for bug #294285.

MIPS fixes: Petar Jovanovic, mips32r2@gmail.com
S390 fixes: Maran, maranp@linux.vnet.ibm.com



git-svn-id: svn://svn.valgrind.org/vex/trunk@2739 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Initial ISA 2.07 support for POWER8-tuned libc

The IBM Power ISA 2.07 has been published on power.org, and IBM's new POWER8
processor is under development to implement that ISA. This patch provides
initial VEX support for running Valgrind on POWER8 systems running a soon-to-be
released Linux distribution. This Linux distro will include a POWER8-tuned
libc that uses a subset of the new instructions from ISA 2.07. Since virtually
all applications link with libc, it would be impossible to run an application
under Valgrind on this distro without adding support for these new instructions
to Valgrind, so that's the intent of this patch. Note that applications built
on this distro will *not* employ new POWER8 instructions by default. There are
roughly 150 new instructions in the Power ISA 2.07, including hardware
transaction management (HTM). Support for these new instructions (modulo the
subset included in this bug) will be added to Valgrind in a phased approach,
similar to what we did for Power ISA 2.06.

Bugzilla 322294

git-svn-id: svn://svn.valgrind.org/vex/trunk@2740 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips32/mips64: Fix compiler warnings.

Fix some compiler warnings when compiling Valgrind for no mips arch.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2741 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Eliminate IRExprP__VECRET and IRExprP__BBPTR and introduce two new
IRExpr kinds instead: Iex_VECRET and Iex_BBPTR. Add constructor 
functions and adjust ppIRExpr, typeOfIRxpr and deepCopyExpr. The
rest is mechanics.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2742 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add support for 256-bit return values for dirty helpers (amd64 only).
(Patrick J. LoPresti, lopresti@gmail.com).  Bug 294285.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2743 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: Fix a problem with CCall.retty type.

Fix a problem when CCall needs to return 64 bits
for return type.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2744 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Support mmxext (integer sse) subset on i386 (athlon).

Some processors like the AMD Athlon "Classic" support mmxext,
a sse1 subset. This subset is not properly detected by VEX.
The subset uses the same encoding as the sse1 instructions.

The subset is described at:
  http://support.amd.com/us/Embedded_TechDocs/22466.pdf
  https://en.wikipedia.org/wiki/3DNow!#3DNow.21_extensions

This introduces a new VEX_HWCAPS_X86_MMXEXT that sits between
the baseline (0) and VEX_HWCAPS_X86_SSE1. There is also a new
x86g_dirtyhelper_CPUID_mmxext to mimics a Athlon "Classic"
(Model 2, K75 "Pluto/Orion").

Groups all mmxext instructions together in one block.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2745 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add algebraic simplifications for Iop_And64 (same as for Iop_And32).
Remove isOnesU32 which is no longer needed.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2746 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Add an optimisation for Iop_Left64.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2747 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Comment-only change.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2748 8f6e269a-dfd6-0310-a8e1-e2731360e62c