ARM: 6272/1: Convert L2x0 to use the IO relaxed operations

This patch is in preparation for a subsequent patch which adds barriers
to the I/O accessors. Since the mandatory barriers may do an L2 cache
sync, this patch avoids a recursive call into l2x0_cache_sync() via the
write*() accessors and wmb() and a call into l2x0_cache_sync() with the
l2x0_lock held.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[pratikp@codeaurora.org: skip l2x0_init changes due to code divergence]
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
(cherry picked from commit 19b8e9fef502b4d9435fe90ba0a442e2c0b91b2f)

Change-Id: Ia479d93593ec4216b3430ef8d1a1c0e353be6ac0
Signed-off-by: Sunil Joseph <sunilj@codeaurora.org>
ARM: mm: cache-l2x0: Change remaining readl/writel's to relaxed variants

This fixes performance issues with graphics (reduced fps) while running
powerlift test case in mdp composition mode and high cpu utilization
during camcorder recording due to pmem cache invalidation taking longer.

Also add memory barrier at the end of l2x0_init, l2x0_inv_range_atomic,
l2x0_clean_range_atomic, l2x0_flush_range_atomic and l2x0_resume to
prevent potential reordering issues.

CRs-Fixed: 265599
CRs-Fixed: 256224
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
(cherry picked from commit a897cf4a8a689ac1a24ac0cbfd0f1edc9132a1f8)

Change-Id: I75961c7ce56f988bbcb0b51e11da867501e7c015

Signed-off-by: Sunil Joseph <sunilj@codeaurora.org>