icache: fix invalidate while refill bug

When an invalidate signal would occur at the same time as a
refill is ongoing, the invalidate address would leak out on
ibus, potentially causing a bus error.
immu: line up input/output port declarations

No functional change.
immu: ack all spr accesses to the immu spr group

Any accesses to not implemented sprs would otherwise lock up
the pipeline, since it nowdays expects spr accesses to be acked.
Reads from not implemented sprs return 0, and writes are nops.
dmmu: line up input/output port declarations

No functional change.
dmmu: ack all spr accesses to the immu spr group

Any accesses to not implemented sprs would otherwise lock up
the pipeline, since it nowdays expects spr accesses to be acked.
Reads from not implemented sprs return 0, and writes are nops.
immu: add support for hardware tlb reload

Instead of generating tlb miss exceptions, walk the page tables
automatically.

It should be noted that instead of following the arch
specification on the layout of the page table entries (PTE),
the layout specified by the openrisc Linux port has been used.
The most notable difference is that in the arch specification,
it is stated that the protection bits should be looked up from a table,
and an index to that table should be in the PTE.
In Linux, the protection bits are instead embedded directly in
the PTE.
cappuccino/lsu: use fsm to control external bus accesses

Gives a bit more control over when and how the external bus
accesses are initiated.
Main motivation is for upcoming support for dmmu hw tlb reloads,
where the actual bus access will take place here in the lsu.
It also makes it more in line how things are done in the fetcher,
and enables the possibility to move the cache refill bus access
logic from the cache into the lsu.
dmmu: add support for hardware tlb reload

Instead of generating tlb miss exceptions, walk the page tables
automatically.

It should be noted that instead of following the arch
specification on the layout of the page table entries (PTE),
the layout specified by the openrisc Linux port has been used.
The most notable difference is that in the arch specification,
it is stated that the protection bits should be looked up from a table,
and an index to that table should be in the PTE.
In Linux, the protection bits are instead embedded directly in
the PTE.
Propagate FEATURE_xMMU_HW_TLB_RELOAD to top level
add avalon bus interface
mmu: hardware reload pte changes

Makes the PTE compliant with the suggestion outlined in
http://lists.openrisc.net/pipermail/openrisc/2013-July/001806.html
Also, properly interpret the L flag and marks the PL1 flag in
the translate register as pointed out is necessary in
http://lists.openrisc.net/pipermail/openrisc/2013-July/001810.html
The actual PL1 flag is not completely implemented yet
and things are still subject to change.
immu: move spr accesses to the first port of tlb dprams

This is to free up the second port to be able to hook-up
huge page indexing to that.
This renames the tlb_reload_busy signal to just busy, since it now
assert on spr accesses also, stalling the fetcher while "wrong"
address is being fetched/written to the tlb.
mmu: fix "typo" in comment about PTEs in PTE table
mmu: remove AUTOINST from match/translate RAMs

There is no benefit to use AUTOINST when all ports of the module
are templated.
mmu: add support for PL1 (aka HUGE) bit

The tlb match and translate registered are both speculatively
read with bith a 8kb page size [set_size+13:13] and a 16 MB page size
[set_size+24:24] index from the virtual address.
If the one read with the 16 MB page size has the PL1
(aka HUGE) bit set, this one is used.
cappuccino/fetch: prevent instructions to propagate on tlb miss/pagefault

Set the instruction passed to decode stage to a nop, to ensure
no side-effects occur while the exception travels along the
pipeline.
immu: register spr read result for stalled accesses

The result from the translate and match registers will only be
available for one clock cycle when spr accesses them,
so in case the spr access is prolonged, the result needs to
be registered.
immu: separate busy and tlb_reload_busy signals

There are a few corner cases where those signals have to be used
separately in the fetcher.
Also, assert busy_o on both the first cycle CS is asserted and
the first ack cycle (which is the cycle after the first CS cycle).
I.e. assert it on the two first cycles of the access.
immu: prevent tlb_miss from being signaled when busy is asserted
dcache: prevent dbus_we_o from toggling independent from dbus_req_o