msm_fb: Avoid multiple disable calls for vsync interrupt

For LCDC and DSI Video mode panels, there seem to be multiple
disable calls for Vsync interrupt term. Change to avoid this
issue by proper synchronization of vsync term and DMA term.

Change-Id: Iaf11ba92cc7db55c6196add2d7dea581cb29fc8a
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm_fb: Handle histogram IRQ cleanly during suspend/resume

Currently, if the histogram disable IOCTL comes after panel
is turned off, we early return the IOCTL causing the interrupt
to be left enabled. This causes IPC issues during suspend. Fix
this issue by properly enabling/disabling the histogram interrupt
during suspend/resume scenario.

Change-Id: I4d38776a43ea854aff3c10c8d9d5450af1d98c91
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
msm: kgsl: Restore the value of RB_BC_CONTROL on context switch

On 8x25Q, when GPU footswitch is turned off during TCXO shutdown, the
RB_BC_CONTROL register value is lost which causes GPU hang after coming
out of TCXO shutdown. Now the value of RB_BC_CONTROL is preserved properly
during context save and restore.

(cherry picked from commit 6b761ba560847bd7df4c6ff9de87bd6298d4b6e2)

Change-Id: I1999f88a5416445568c4b63ca0b99233551258f4
CRs-fixed: 441134
Signed-off-by: Vinay Roy <vroy@codeaurora.org>
msm_fb : display : Block RGB downscale in MDP 4.0 and 4.1

Downscale is not allowed on RGB pipes in MDP 4.0 and 4.1. Hence,
fail the OVERLAY_SET ioctl for such configurations.

Signed-off-by: Pradeep Jilagam <pjilagam@codeaurora.org>
(cherry picked from commit 3545573720822ce97ec37586f10fdf74a6d4f090)

Change-Id: I8445c18ac21cb7322eb9eb4c802623df5da07eb7
Signed-off-by: Gopal Goberu <ggober@codeaurora.org>
USB: msm72k_udc: Don't handle asynchronous interrupt

USB enter low power mode after detecting the wall charger. When
wall-charger is disconnected, USB hardware generate asynchronous interrupt
for notifying B-Session Valid low condition. OTG and UDC share the same
interrupt line. The OTG interrupt handler is called first and it disable
the IRQ and schedule the resume work. As the interrupt is received,
the kernel will invoke all shared interrupt handlers though the IRQ is
disabled by the first handler.

The UDC interrupt handler is accessing USB registers before clocks are
turned on. Avoid unclocked access by ignoring the asynchronous interrupt.

CRs-Fixed: 442012
Change-Id: I58c6a6e192ce274ab265b5d7c8d95ad84dc55efd
Signed-off-by: Rajkumar Raghupathy <raghup@codeaurora.org>
video: msm: Check for null in LCDC IRQ handler