[mips] Expand pseudo load, store and copy instructions right before
callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178391 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178392 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178393 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178394 91177308-0d34-0410-b5e6-96231b3b80d8
Fix indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178395 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178396 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.

The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.

We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178405 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix DSP instructions to have explicit accumulator register operands.

Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8