hdl/top/ml_605/*/*.xcf: add xcf constraints file

Correctly constrained some high fanout paths
hdl/modules/*/wb_acq_core/wbgen/: update wbgen files

Added register for selecting the next acquisition
channel to be acquired
hdl/sim/regs/wb_acq_core_regs.vh: update register definitions
hdl/modules/pcie/*: add DDR3 debug signals

These signal let us tap directly into the ddr3 memory
controller signals
hdl/modules/*/wb_acq_core/wbgen/*: reduce acq_chan width

Now we have a width of 5 for this field, allowing us
to multiplex up to 32 channels (to the masx of 128-bit each)
hdl/sim/regs/*: update acq_core register definitions
hdl/modules/*/wb_acq_core/*: (1/8) add acq_core support for multiple channels

This adds a few records and functions to be used in the
multiple channel support acq_core
hdl/modules/*/wb_acq_core/*: (2/8) add acq_core support for multiple
channels

Change interface of top modules to support multiple channels
hdl/modules/*/wb_acq_core/*: (3/8) add acq_core support for multiple
channels

Main support to multiple channels comes from the ddr3
interface. With this patch it is possible to perform
aggregations of 2, 4, or 8 of input data words (64 or 128-bit)
into the memory controller (256 or 512-bit)

Also, added simple support for simulation (acq_ddr3_read.vhd)
hdl/modules/*/wb_acq_core/*: (4/8) add acq_core support for multiple
channels

Update top modules definitions in dbe_wishbone package
hdl/modules/*/wb_acq_core/*: (5/8) add acq_core support for multiple
channels

Add wrapper to top module to allow simulation with verilog.
The wb_acq_core module should have done this, but its interface
is more convinient than a plain one.

Also, update Manifest to include this module
hdl/sim/*/wb_acq_core/*: (6/8) add acq_core support for multiple
channels

Update verilog testbench and waveform
hdl/top/*/wb_acq_core/*: (7/8) add acq_core support for multiple
channels

Update top example file to test the multiple channel approach.
Effectivelly, we just offset by a certain amount the adc values
and plug them ito different channels.

With this, we can compare its values and validate the multiple
channel approach.

Also, commented out the AREA contraints in the .ucf file, as
it causes timing to fail, sometimes.
hdl/syn/*/wb_acq_core/*: (8/8) add acq_core support for multiple
channels

Update synthesis files