Make DWARFCompileUnit non-copyable

Summary:
This is a part of D1164. DWARFCompileUnit is not that lightweight
to copy it around, and we want it to own corresponding .dwo compile unit
eventually.

Reviewers: echristo

Reviewed By: echristo

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1298

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189089 91177308-0d34-0410-b5e6-96231b3b80d8
80 cols

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189091 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: make sure ARM-mode pseudo-inst requires IsARM

I'd forgotten that "Requires" blocks override rather than add to the
constraints, so my pseudo-instruction was being selected in Thumb mode leading
to nonsense instructions.

rdar://problem/14817358

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8
Turn MipsOptimizeMathLibCalls into a target-independent scalar transform

...so that it can be used for z too.  Most of the code is the same.
The only real change is to use TargetTransformInfo to test when a sqrt
instruction is available.

The pass is opt-in because at the moment it only handles sqrt.


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[SystemZ] Prefer LHI;ST... over LAY;MV...

If we had a store of an integer to memory, and the integer and store size
were suitable for a form of MV..., we used MV... no matter what.  We could
then have sequences like:

    lay %r2, 0(%r3,%r4)
    mvi 0(%r2), 4

In these cases it seems better to force the constant into a register
and use a normal store:

    lhi %r2, 4
    stc %r2, 0(%r3, %r4)

since %r2 is more likely to be hoisted and is easier to rematerialize.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189098 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Try reversing comparisons whose first operand is in memory

This allows us to make more use of the many compare reg,mem instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189099 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Add basic prefetch support

Just the instructions and intrinsics for now.


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Add function attribute 'optnone'.

This function attribute indicates that the function is not optimized
by any optimization or code generator passes with the 
exception of interprocedural optimization passes.



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[ARMv8] Add CodeGen for VMAXNM/VMINNM.


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[msan] Fix handling of va_arg overflow area on x86_64.

The code was erroneously reading overflow area shadow from the TLS slot,
bypassing the local copy. Reading shadow directly from TLS is wrong, because
it can be overwritten by a nested vararg call, if that happens before va_start.



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[mips][msa] Few MSA Builtins have side-effects. Added IntrNoMem to those that don't.



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[ARM] Fix another ARM FastISel -verify-machineinstrs issue.


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Checking commit access; added one space

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