altera pcie: include in Manifest for hdlmake
altera pcie: leave generated SDC constraints as a reference only
serial_lcd: WB interface to LCD displays with serial protocol
wb_pcie: include only on Altera
serial_lcd: generic clock and row timings
altera pcie: do not reset PCIe when no slave bus is connected
lm32: add missing wires to silence warnings

In Verilog, an "assign x = y;" will cause a warning in Quartus if x was not defined.
For example,
  Warning (10236): Verilog HDL Implicit Net warning at lm32_allprofiles.v(45398): created implicit net for "multiply"
This patch defines all such nets.

Also, the CSR width is too narrow by default (CFG2 must fit).
lm32: remove unused signals

Some signals are flat-out unused
 => these are outright removed
Some signals are used only under certain conditions
 => these have the definitions made also conditional
lm32: one too many watch points => undefined warning
lm32: prevent truncation warnings by explicitly selecting low bits
lm32: eliminate truncation warnings and make EBA_RESET a parameter

CFG_EBA_RESET is supposed to be the default value of the LM32's eba_reset
parameter. Unfortunately, the constant leaked into the sources directly.

In order to clean-up a truncation warning for pc_f, it was easiest to fix
the missing parameter and then use a subarray of that value.
altera fifos: remove unused warnings

There were many constructs like this:
  gen_with_empty : if(g_with_empty) generate
    empty_o <= empty;
  end generate gen_with_empty;

If g_with_empty is true, then there are no warnings.
If g_with_empty is false, then empty_o is unset and empty is unused.

There is no improvement in performance/resource utilization to explicitly
cutting these signals. The optimizer will happily discard unused logic.

The alternative of adding
  gen_without_empty : if(not g_with_empty) generate
    empty_o <= 'X';
  end generate gen_without_empty;
will remove the empty_o unset warning, but not the empty unused warning.

This patch does make it possible for designs to  use empty_o without
setting g_with_empty; an error. On the other hand, those designs had
undefined behaviour before anyway, so they might have worked unreliably.
gc_crc_gen: remove unused signals
gc_wfifo: eliminate null range warnings when no sync chain used
wb_slave_adapater: connect missing master output ports
altera rams: use a default initial value of '0' to avoid hundreds of warnings
altera pcie: tweak generated files to eliminate warnings
lm32: off-by-one in memory initialization
genrams: remove init_value generic option

In the past we used a generic to set the initial memory contents on altera.
Unfortunately, quartus compiles big generics slowly (read: hours).
Now we can load from a .mif file instead, which is much faster (seconds).
Thus, this old option is no longer needed.
genram: add a generic_simple_dpram

On both Altera and Xilinx, a dual port memory can achieve twice the
bit-width per memory block when there is a single reader and writer.
This adds a place-holder generic_simple_dpram for Xilinx so that code
using the purpose-built variant for Altera continues to work on ISE.