Modified sync_gen_init.m to use scale parameter. Previously block parameter was ignored.
Merge pull request #11 from oxfork/casper_vanilla

Modified sync_gen_init.m to use scale parameter. Previously block parame...
adc_sim, of, conv, of_detect_bus readd

cleanup commit c77818c broke adc083000x2. Added blocks back to ADCs
section.
(cherry picked from commit 2e8fc419fdb5829073d6a2796edb45d4772c7182)
update library location

It seems there was an idea to create an adc_lib and some blocks were
moved there, but the move was abandoned part way through.
(cherry picked from commit f73dbe2ba75da27789075c129c730d4e3b47b9cf)
adc083000 script clean-ups

removed references to adc_lib.
replaced reuse_line with add_line.
replaced 'simulink/Sources/In1' with 'built-in/Inport'
replaced 'simulink/Sinks/Out1' with 'built-in/Outport'
(cherry picked from commit 88da838af063cbf91da5e7b1edc044463e7cf64e)
Compare block locations in lower case

The input block location should be converted to lower case as well as the
location found for the block with the same name. (thanks Glen)
(cherry picked from commit afa12d6608c65b09d44b1dc2d15ff5047b9bdf78)
Path correction in adc_sim_init.m

This was preventing the script from running correctly.
Add design files for ADC16 (aka adcleda)
Force ADC16 adc_brd param to lowercase

This allows the mask to show uppercase even though the scripts work with
lowercase.
Merge remote branch 'casper/master' into merge-branch
Merge remote branch 'ska-sa/master' into merge-branch
Merge commit '3cacb20' into adc16-branch
Move ADC16 pcores from xps_lib to xps_base
Merge branch 'adc16-branch' into merge-branch

Conflicts:
	xps_base/XPS_ROACH2_base/core_info.tab
	xps_library/gen_xps_files.m
Rename adcleda to adc16

adcleda was the early development name, but adc16 is the real name.
Set undefined XILINX_PATH from XILINX variable

If XILINX_PATH is undefined, set it based on the value of the XILINX variable
(stripping off any '/ISE' suffix).
Get undefined XPS_BASE_PATH from MLIB_DEVEL_PATH

If XPS_BASE_PATH is defined use it, but if it is not defined then use the value
of "${MLIB_DEVEL_PATH}/xps_base".
Add 13.3 to the list of supported sysgen versions
Add comments to opb_adc16_controller pcore verilog

These comments describe the bit assignments in the two registers supported by
the opb_adc16_controller pcore.

Some whitespace was added to HDL code for prettier looking code blocks.
Add constraints to ADC16 3-wire interface signals

Specify LVCMOS15, SLOW slew rate, and 2 mA (minimum) drive current.