Merge branch 'master' of https://github.com/ispc/ispc into constfold
Improve warnings for right shift by varying amounts.

Fixes:
- Don't issue a warning when the shift is a by the same amount in all
  vector lanes.
- Do issue a warning when it's a compile-time constant but the values
  are different in different lanes.

Previously, we warned iff the shift amount wasn't a compile-time constant.
Add support for fast division of varying int values by small constants.
    
For varying int8/16/32 types, divides by small constants can be
implemented efficiently through multiplies and shifts with integer
types of twice the bit-width; this commit adds this optimization.
    
(Implementation is based on Halide.)
Add support for mask vectors of 8 and 16-bit element types.

There were a number of places throughout the system that assumed that the
execution mask would only have either 32-bit or 1-bit elements.  This
commit makes it possible to have a target with an 8- or 16-bit mask.
Reduce estimated costs for 8 and 16-bit min() and max() in stdlib.

These actually compile to a single instruction.
Choose type for integer literals to match the target mask size (if possible).

On a target with a 16-bit mask (for example), we would choose the type
of an integer literal "1024" to be an int16.  Previously, we used an int32,
which is a worse fit and leads to less efficient code than an int16
on a 16-bit mask target.  (However, we'd still give an integer literal
1000000 the type int32, even in a 16-bit target.)

Updated the tests to still pass with 8 and 16-bit targets, given this
change.
Fix bug in lGetConstantInt() in parse.yy.

Previously, we weren't handling signed/unsigned constant types correctly.
Use @llvm.readcyclecounter to implement stdlib clock() function.

Also added a test for the clock builtin.
Add SSE4 target optimized for computation with 8-bit datatypes.

This change adds a new 'sse4-8' target, where programCount is 16 and
the mask element size is 8-bits.  (i.e. the most appropriate sizing of
the mask for SIMD computation with 8-bit datatypes.)
Fix bug in lEmitVaryingSelect() for targets with i1 mask types.

Commit 53414f12e6c introduced a but where lEmitVaryingSelect() would
try to truncate a vector of i1s to a vector of i1s, which in turn
made LLVM's IR analyzer unhappy.
Add SSE4-16 target.

Along the lines of sse4-8, this is an 8-wide target for SSE4, using
16-bit elements for the mask.  It's thus (in principle) the best
target for SIMD computation with 16-bit datatypes.
Improved optimization of vector select instructions.

Various LLVM optimization passes are turning code like:

%cmp = icmp lt <8 x i32> %foo, %bar
%cmp32 = sext <8 x i1> %cmp to <8 x i32>
. . .
%cmp1 = trunc <8 x i32> %cmp32 to <8 x i1>
%result = select <8 x i1> %cmp1, . . .

Into:

%cmp = icmp lt <8 x i32> %foo, %bar
%cmp32 = zext <8 x i1> %cmp to <8 x i32>   # note: zext
. . .
%cmp1 = icmp ne <8 x i32> %cmp32, zeroinitializer
%result = select <8 x i1> %cmp1, …

Which in turn isn't matched well by the LLVM code generators, which
in turn leads to fairly inefficient code.  (i.e. it doesn't just emit
a vector compare and blend instruction.)

Also, renamed VSelMovmskOptPass to InstructionSimplifyPass to better
describe its functionality.
Explicitly call the PBLENDVB intrinsic for i8 blending with sse4-8.

This is slightly cleaner than trunc-ing the i8 mask to i1 and using
a vector select.  (And is probably more safe in terms of good code.)
Add reduce_add() for int8 and int16 types.

This maps to specialized instructions (e.g. PSADBW) when available.
InterlockedAdd -> InterlockedExchangeAdd for better portability (InterlockedAdd is not always supported)
Add 8-bit and 16-bit specialized NEON targets.

Like SSE4-8 and SSE4-16, these use 8-bit and 16-bit values for mask
elements, respectively, and thus should generate the best code when used
for computation with datatypes of those sizes.
Remove __pause from stdlib_core() in utils.m4.

It wasn't ever being used, and was breaking compilation on ARM.
Renaming mandelbrot_tasks files to be different from mandelbrot
Merge branch 'master' into arm
Remove support for building with LLVM 3.1