Fix PPU frame timing on even/odd frames
Enable cycle based timing
Mirror memory mapped PPU registers

"These nominally sit at $2000 through $2007 in the CPU's address space, but because they're incompletely decoded, they're mirrored in every 8 bytes from $2008 through $3FFF, so a write to $3456 is the same as a write to $2006."

-- http://wiki.nesdev.com/w/index.php/PPU_registers
PPU cycles are 1-indexed (doh!), not 0-indexed

Last cycle needs to be 341 so that each scan line gets 340 cycles.

Stupid off-by-one errors
Don't generate NMI when when setting enable many times
Delay NMI handling by one instruction if it's emitted on the last cycle of the current instruction
Skip VBL when PPUSTATUS is read in some cases
More accurately handle canceling NMI via reading PPUSTATUS.

Makes sense just to emulate the behavior:

"Reading $2002 within a few PPU clocks of when VBL is set results in special-case behavior. Reading one PPU clock before reads it as clear and never sets the flag or generates NMI for that frame. Reading on the same PPU clock or one later reads it as set, clears it, and suppresses the NMI for that frame. Reading two or more PPU clocks before/after it's set behaves normally (reads flag's value, clears it, and doesn't affect NMI operation). This suppression behavior is due to the $2002 read pulling the NMI line back up too quickly after it drops (NMI is active low) for the CPU to see it. (CPU inputs like NMI are sampled each clock.)"