Add two new MIPS CPU families - mips24k and mips74k.

They're both different cores:

* mips24k is an 8-stage pipeline, mips32r1 ABI, non-superscalar core.
* mips74k is a dual-issue 15-stage superscalar design, mips32r2 ABI.

They have different sets of quirks and bugs; these #define entries
will be used to work around these.

Now, strictly speaking, we should have CPU ABI families (mips32r1, mips32r2,
etc) and CPU core types (mips4k, mips24k, mips74k, etc.)  But this is the
starting point of that particular tidy-up.

Reviewed by:	imp@
Approved by:	re@ (gjb)
Shuffle the includes around so they occur after opt_global.h is included;
this way the CPU ABI / core #define items are there.

Reviewed by:	imp@
Approved by:	re@ (gjb)
Add "better" MIPS24k and MIPS74k barriers.

* the mips74k cores only need EHB (which is 'sll $0, $0, 3')
  here; NOPs don't actually work.

* add EHB as the last NOP for the default barriers/hazards;
  that is "better" behaviour and should work on a wider
  variety of processors.

This allows the existing (icky) TLB code to work, allowing
the AR9344 SoC (mips74k) to actually get through kernel startup.

Tested:

* AR9344 SoC - (mips74k)
* AR9331 SoC - (mips24k)

TODO:

* test on mips4k CPUs, just to be sure.

* document that sll $0, $0, 3 is actually "EHB" and that it
  falls back to being a NOP for pre-mips32r1.

* mips24k has an errata that we currently don't correctly explicitly
  state - ie, that after DERET/ERET, the only valid instruction is
  a NOP.

Reviewed by:	imp@
Approved by:	re@ (gjb)
Mark AR934x based boards to be mips74k.

Reviewed by:	imp@
Approved by:	re@ (gjb)