fixed symmetry for top
[logisim] added top with test mode
[logisim] added 8 bit test mode circuit
[logisim] changed signal name
[vhdl] removed components, using entity instantiation
[vhdl] removed t_en signal and added signals for test mode
[vhdl] changed signal assignments and 'a' and 'b' row level
[vhdl] added test mode in top
[vhdl] initial commit of shift slice module
[rtl] added/modified rtl pics
[rtl] removed old lut slice rtl pic