intermediate checkin
intermediate checkin
intermediate checkin
genxprojfrombsv runs to completion
remving busdefs
generated bsv is now complete.  I need to generate pragmas which reduce the number of scheduler warnings
fix errors/warnings in generated bsv
able to generate bitfiles for zedboard'
bsim now builds
bring memcpy HW into the new regime
memcpy bsim top
echo2proj android eecutable compiles
new implementation of directory as regfile
echo2 works in bsim
fixed some tricky timing bugs involving the implementation and use of the ready queue.  these were causing incoherence between the interrupt and queue status.  When running both in BSIM and on the Zynq platform I always see at leaset one non-zero queue status when the shared interrupt is asserted.  Sadly, the tests still wedge the zynq platform.  I think there is some kernel magic involving shared interrupts that I am not aware of
simplify use of priority queue
disabling interrupts so the new HW works on the zynq platform.  After updating the tests I will continue to work on (and hopefully reenable) the interrupts
memcopy works in simulation