omap: cpu: cpuidle: correct idle states for exit latency and tresholds

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Cstatesexit_latencythresholds
OMAP4430CPUsMPUCoreususSystemClock
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C1WFIONON44ON
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C2OFFINAINA300300ON
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C3OFFCSWROSWR500010000OFF
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C4OFFOSWROSWR520035000OFF
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Cstatesexit_latencythresholds
OMAP4460CPUsMPUCoreususSystemClock
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C1WFIONON44ON
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C2OFFINAINA3001800ON
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C3OFFCSWROSWR40004000OFF
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C4OFFOSWROSWR42004200OFF
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Cstatesexit_latencythresholds
OMAP4470CPUsMPUCoreususSystemClock
------------------------------------------------------------------------------------
C1WFIONON44ON
------------------------------------------------------------------------------------
C2OFFINAINA5001200ON
------------------------------------------------------------------------------------
C3OFFCSWROSWR53005300OFF
------------------------------------------------------------------------------------
C4OFFOSWROSWR550015000OFF
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I/O, writeback: More less dirty throttling, filesystem writeback from page reclaim reduced

- This is a backport from 3.2
I/O, writeback: More less dirty throttling, filesystem writeback from page reclaim reduced - PART 2

- This is a backport from 3.2
staging: android: lowmemorykiller: Additions, fixes due to 3.4 backport
omap: pm: move MPU PRCM interrupt event to perform before clearing source events
defconfig: CONFIG_HZ / CONFIG_OMAP_32K_TIMER_HZ = 300
ARM: 7168/1: use of cache type function for 'arch_get_unmapped_area'

We use the existingcache type decoding function instead of custom decoder which works only for ARMv6
defconfig: configure JRCU, build performance gov as a module§
kernel: sched: overhead of obtain facotr reduced

Smart wake-affine is using node-size as the factor, but the overhead of
mask operation is high.

Thus, this patch introduce the 'sd_llc_size', which will record the highest
cache-share domain size, and make it to be the new factor, in order to
reduce the overhead and make more reasonable.

And we suppose it will benefit a lot when facing a huge platform.

Test:
Tested with 12 cpu X86 server and tip 3.10.0-rc7.

pgbench    basesmart + optimization

| db_size | clients |  tps  ||  tps  |
+---------+---------+-------+   +-------+
| 22 MB   |       1 | 10598 |   | 10781 |
| 22 MB   |       2 | 21257 |   | 21328 |
| 22 MB   |       4 | 41386 |   | 41622 |
| 22 MB   |       8 | 51253 |   | 60351 |
| 22 MB   |      12 | 48570 |   | 54255 |
| 22 MB   |      16 | 46748 |   | 55534 | +18.79%
| 22 MB   |      24 | 44346 |   | 55976 | +26.23%
| 22 MB   |      32 | 43460 |   | 55279 | +27.20%
| 7484 MB |       1 |  8951 |   |  9054 |
| 7484 MB |       2 | 19233 |   | 19252 |
| 7484 MB |       4 | 37239 |   | 37354 |
| 7484 MB |       8 | 46087 |   | 51218 |
| 7484 MB |      12 | 42054 |   | 49510 |
| 7484 MB |      16 | 40765 |   | 52151 | +27.93%
| 7484 MB |      24 | 37651 |   | 52720 | +40.02%
| 7484 MB |      32 | 37056 |   | 51094 | +37.88%
| 15 GB   |       1 |  8845 |   |  9139 |
| 15 GB   |       2 | 19094 |   | 19379 |
| 15 GB   |       4 | 36979 |   | 37077 |
| 15 GB   |       8 | 46087 |   | 50490 |
| 15 GB   |      12 | 41901 |   | 48235 |
| 15 GB   |      16 | 40147 |   | 51878 | +29.22%
| 15 GB   |      24 | 37250 |   | 52676 | +41.41%
| 15 GB   |      32 | 36470 |   | 50198 | +37.64%
CC: Ingo Molnar <mingo@kernel.org>
CC: Peter Zijlstra <peterz@infradead.org>
CC: Mike Galbraith <efault@gmx.de>
Signed-off-by: Michael Wang <wangyun@linux.vnet.ibm.com>
kernel: sched: added smart wake-affine foundation

This one was missing for the prior commit!

wake-affine stuff is always trying to pull wakee close to waker, by theory,
this will bring benefit if waker's cpu cached hot data for wakee, or the
extreme ping-pong case.

And testing show it could benefit hackbench 15% at most.

However, the whole stuff is somewhat blindly and time-consuming, some
workload therefore suffer.

And testing show it could damage pgbench 50% at most.

Thus, wake-affine stuff should be more smart, and realise when to stop
it's thankless effort.

This patch introduced 'nr_wakee_switch', which will be increased each
time the task switch it's wakee.

So a high 'nr_wakee_switch' means the task has more than one wakee, and
bigger the number, higher the wakeup frequency.

Now when making the decision on whether to pull or not, pay attention on
the wakee with a high 'nr_wakee_switch', pull such task may benefit wakee,
but also imply that waker will face cruel competition later, it could be
very cruel or very fast depends on the story behind 'nr_wakee_switch',
whatever, waker therefore suffer.

Furthermore, if waker also has a high 'nr_wakee_switch', imply that multiple
tasks rely on it, then waker's higher latency will damage all of them, pull
wakee seems to be a bad deal.

Thus, when 'waker->nr_wakee_switch / wakee->nr_wakee_switch' become higher
and higher, the deal seems to be worse and worse.

The patch therefore help wake-affine stuff to stop it's work when:

wakee->nr_wakee_switch > factor &&
waker->nr_wakee_switch > (factor * wakee->nr_wakee_switch)
The factor here is the node-size of current-cpu, so bigger node will lead
to more pull since the trial become more severe.

After applied the patch, pgbench show 40% improvement at most.

Test:
Tested with 12 cpu X86 server and tip 3.10.0-rc7.

pgbench    basesmart

| db_size | clients |  tps  ||  tps  |
+---------+---------+-------+   +-------+
| 22 MB   |       1 | 10598 |   | 10796 |
| 22 MB   |       2 | 21257 |   | 21336 |
| 22 MB   |       4 | 41386 |   | 41622 |
| 22 MB   |       8 | 51253 |   | 57932 |
| 22 MB   |      12 | 48570 |   | 54000 |
| 22 MB   |      16 | 46748 |   | 55982 | +19.75%
| 22 MB   |      24 | 44346 |   | 55847 | +25.93%
| 22 MB   |      32 | 43460 |   | 54614 | +25.66%
| 7484 MB |       1 |  8951 |   |  9193 |
| 7484 MB |       2 | 19233 |   | 19240 |
| 7484 MB |       4 | 37239 |   | 37302 |
| 7484 MB |       8 | 46087 |   | 50018 |
| 7484 MB |      12 | 42054 |   | 48763 |
| 7484 MB |      16 | 40765 |   | 51633 | +26.66%
| 7484 MB |      24 | 37651 |   | 52377 | +39.11%
| 7484 MB |      32 | 37056 |   | 51108 | +37.92%
| 15 GB   |       1 |  8845 |   |  9104 |
| 15 GB   |       2 | 19094 |   | 19162 |
| 15 GB   |       4 | 36979 |   | 36983 |
| 15 GB   |       8 | 46087 |   | 49977 |
| 15 GB   |      12 | 41901 |   | 48591 |
| 15 GB   |      16 | 40147 |   | 50651 | +26.16%
| 15 GB   |      24 | 37250 |   | 52365 | +40.58%
| 15 GB   |      32 | 36470 |   | 50015 | +37.14%
CC: Ingo Molnar <mingo@kernel.org>
CC: Peter Zijlstra <peterz@infradead.org>
CC: Mike Galbraith <efault@gmx.de>
Signed-off-by: Michael Wang <wangyun@linux.vnet.ibm.com>
mm: vmalloc: Use wrapper function 'get_vm_area_size' for calculating size of vm area
mm: vmalloc: fix typo
mm: vmalloc: fixes and additions for prior commit(s)
ARM: cacheflush: disable address range round up to nearest page

The flush_cache_user_range macro takes a pair of addresses describing
the start and end of the virtual address range to flush. Due to an
accidental oversight when flush_cache_range_user was introduced, the
address range was rounded up so that the start and end addresses were
page-aligned.CCCC
ARM: cacheflush: traps: no more rounding to nearest vma
ARM: cacheflush: added iovec-based cache flush system call

This introduces a private system call for ARM, cacheflush_iov, which processes a range of addresses described in an iovec structure
ARM: cachetype: PIPT l-cache detection using CTR

I-Caches with a PIPT policy are identified by Cache Type Register L1Ip field using encoding 11b.

This addition extends cache policy parsing to identify PIPT I-caches correctly and prevent them from being treated as VIPT aliasing in the case they're sufficiently large
ARM: cacheflush/cachetype: prepare for compile
Makefile: Remove double entry and add Cortex-a9 flag
defconfig: CONFIG_HZ=128