In simulation;  kinda works...

*  I moved the code over to my Spartan-6 project, since this was the easiest way to get it
   to simulate, and it will be in an environment with a good SDRAM simulation.
*  Many changes to the code to get it to parse and make some sense.
*  The cache memory really does need initialization at start up, at least for the simulator.
   So I added a full cache invalidate state which is set at reset.  This loops through the
   entire tag RAM clearing the valid bits.
*  The simulation looks like what you would expect from a cache, with 4 beat accesses and
   the CPU trying to get data, but the wrong data is ending up on the CPU.  There is a bad
   interaction with the stall signals and the address, so the CPU sometimes gets the right
   instruction but often doesn't.
The I-cache works!

*  Changed the interface from the processor.  It now has the early address in addition to the
   current address (the PC), and the Valid signal is now the Enable signal.

   The thinking is that the cache RAM cell needs to load it's read address at the same time as
   the PC would load the address from the ID stage, so Enable from the processor is the same
   signal that loads the PC with the next instruction address.  The block RAM has its own
   registers for the read address, so we need to load them in parallel.  Since the instruction
   RAM in Grant's MIPS model is asynchronous, this works out nicely.