[mips][msa] Improves robustness of the test by enhancing pattern matching.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192446 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.

INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Direct Object Emission for the majority of the ELM instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
This reverts r192449 because of compiler warning generated on darwin build.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
This reverts 192447 because of compiler warning generated on darwin build.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
Tests: Be less dependent on a specific schedule/regalloc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192454 91177308-0d34-0410-b5e6-96231b3b80d8
fix typo in comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192455 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Fix FP ABI attributes with no VFP enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192458 91177308-0d34-0410-b5e6-96231b3b80d8
Better info when debugging vectorizer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192460 91177308-0d34-0410-b5e6-96231b3b80d8
Fix handling of CHECK-DAG inside of CHECK-LABEL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192463 91177308-0d34-0410-b5e6-96231b3b80d8
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
 a = load i64* addr
 b = trunc i64 a to i32
 c = lshr i64 a, 32
 d = trunc i64 c to i32

into:
 b = load i32* addr1
 d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Tests: Be less dependent on a specific schedule/regalloc"

This reverts r192454

Apparently FileCheck isn't as smart as I though and does not enforce a
topological order between variable defs+uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192472 91177308-0d34-0410-b5e6-96231b3b80d8
[DAGCombiner] Revert load slicing (r192471), until I figure out why it fails on ubuntu.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
[DAGCombiner] Reapply load slicing (192471) with a test that explicitly set sse4.2 support.
This should fix the buildbots.

Original commit message:
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32

into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
Really fix CHECK-LABEL and CHECK-DAG interaction. This actually just restores the initial implementation that was in r186162 but got lost in some subsequent refactoring. More explicit variable names and comments are present now to hopefully prevent repeat regression, as well as another test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192477 91177308-0d34-0410-b5e6-96231b3b80d8
Debug Info Testing Case: check for the name of a structure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192478 91177308-0d34-0410-b5e6-96231b3b80d8
Add warning about CHECK-DAG with variable definition

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192479 91177308-0d34-0410-b5e6-96231b3b80d8
[DAGCombiner] Load slicing test case: attempt to really fix the buildbots (used sse4.2 instead of avx!).

<rdar://problem/14477220>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192480 91177308-0d34-0410-b5e6-96231b3b80d8
Introduce ad hoc liveness tracking utility: LiveRegUnits

Contains a set of live register (units) and code to move forward and
backward in the schedule while updating the live set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192481 91177308-0d34-0410-b5e6-96231b3b80d8
Remove kill flags after if conversion if necessary

When if converting something like:
true:
   ... = R0<kill>

false:
   ... = R0<kill>

then the instructions of the true block must not have a <kill> flag
anymore, as the instruction of the false block follow and do still read
the R0 value.
Specifically this patch determines the set of register live-in in the
false block (possibly after simulating the liveness changes of the
duplicated instructions). Each of these live-in registers mustn't be
killed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192482 91177308-0d34-0410-b5e6-96231b3b80d8