krait optimizations from caf

libc: krait: Use performance version of memcpy.

Change-Id: I47d25d1da5b1a96bbc1b60f8acdaa31721a68e73

 This is the 2nd commit message:

libc: krait: Use performance version of bcopy and memmove

Change-Id: I587085aeb0c30ceccaa3f420594a194b129632b5

 This is the 3rd commit message:

libc: krait: Restore prior version of strcmp.

Change-Id: I8ddcdb4d3a905dd746985435dcdb525ab5a1c947

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Bionic/libm: fast neon pow() for small x,y.

Add a fast neon version of pow() suitable for relatively small
positive x and y (between 0 and 4).  Run the standard
implementation in all other cases.  Gives approximately 60%
performance improvement to AnTuTu FPU scores

Change-Id: I97e0712daeb2740764b26a44be0caaa39c481453

 This is the 5th commit message:

Bionic/libm: Prefer branches and VFP ABI.

For internal functions set gcc attribute "aapcs-vfp" for ARM
and use -fno-if-conversion to prefer branches over predicated
instructions (improves performance on architectures with good
branch prediction).

Change-Id: I8424e0e82a19d35e7e3b6e3e122dcdecdd5426fd

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Bionic/libm: add assembly versions of sin/cos.

Add assembly versions of sin/cos with integrated remainder pi/2
calculation.  Directly extracted from binary libm.so compiled with
__ieee754_rem_pio2 calls inlined.

Change-Id: Ia093f420e58e794635e3a5f09e8236ae7601f1f6

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Bionic/libm: Pow optimizations and bug fixes.

Use VFP calling convention for pow_neon handoff function by default.
Fix register usage collision between two different polynomial
coefficients in pow_neon.  Remove conditional execution in pow_neon
and replace with branching.

Change-Id: I76095f4a006e2fb01a53943b66fd69bfa1fd3033

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Bionic/libm: Add precision-correct de-serialize sin/cos.

Modify sin/cos to improve performance while retaining bit-for-bit
accuracy with existing algorithm.

Change-Id: Iaba2dd731cd015732744705dad8bddb713b43067

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libm: optimistic pow calling.

Call optimized pow optimistically and revert to full range
implementation if we detect an out-of-range input.

Change-Id: I6f3aa734adbf99484b7ff70736ef83a41e5815b8

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libm: sqrt and sqrtf via ARM vsqrt instruction

Optimized sqrt and sqrtf for arm by using hardware
opcode for sqrt rather than generic slow portable
code.

Change-Id: I84694159577aef6418710548085d8149c45e0e3f

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Bionic/libm: Remove extra vmov from sin/cos.

Move integer representations of x bits on the integer side rather
than moving them to and from the FP registers.

Change-Id: I1895db385c9616cdae9ab6403f392dfbae292adc

 This is the 12th commit message:

Bionic/libm: enable optimized math functions on more QCOM targets.

allow more QCOM targets to use optimized math functions.

Change-Id: I76ee1bf951ae1c8397fef3af6e9937ed8cad9b62

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libc: krait: Perform all memmoves as word-wise at minimum

Certain transfers of very small sizes or that end by copying a small
remnant were moving memory a byte at a time.  Perform these using word
operations if 2 or more bytes remain.

Change-Id: Ie0aef8927f7bd452509913d7368e5c71b7be4720

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Revert "libc: krait: Perform all memmoves as word-wise at minimum"
This reverts commit 1fae6403c2c37f21a740c54b8f5451777b6affe1.

Change-Id: Icb80126042c17dc234ce7a6282846ca344db4ee1

 This is the 15th commit message:

libm: krait: Fix build warning for e_pow.o

e_pow.o given more than once in the same rule. Remove extra arm/e_pow.S
reference in libm/Android.mk.
Add new optimized strlen for arm.

This optimized version is primarily targeted at cortex-a15.

Tested on all nexus devices using the system/extras/libc_test strlen test.
Tested alignments from 1 to 32 that are powers of 2.
Tested that strlen does not cross page boundaries at all alignments.

Speed improvements listed below:

cortex-a15
- Sizes >= 32 bytes, ~75% improvement.
- Sizes >= 1024 bytes, ~250% improvement.

cortex-a9
- Sizes >= 32 bytes, ~75% improvement.
- Sizes >= 1024 bytes, ~85% improvement.

krait
- Sizes >= 32 bytes, ~95% improvement.
- Sizes >= 1024 bytes, ~160% improvement.

Merge from internal master.

(cherry-picked from 2fc071797743b88a9a47427d46baed7c7b24f4d2)

Change-Id: I1ceceb4e745fd68e9d946f96d1d42e0cdaff6ccf

Conflicts:
	libc/arch-arm/generic/generic.mk
	libc/arch-arm/krait/krait.mk
Update to latest cortexa15 memcpy code.

This uses the new code original submitted as memcpy.a15.S as
the base. However, the old code handled unaligned src/dst better
so that was spliced in. I optimized the original unaligned code by
removing a few unnecessary instructions. I optimized the a15 code by
rewriting the pre and post code. I also modified the main loop to add
a pld so that larger copies would not stall waiting for memory.

Test cases for the new memcpy:

- Copy all sized values from 0 to 1024 bytes, using whatever alignment
  is returned by malloc.
For each alignment case described below, the test copied from 0 to 128
bytes.
- Src and dst pointers are both aligned to the same value, starting
  at one going through every power of two up to and including 128.
- Src aligned to double word boundary, dst aligned to word boundary.
- Src aligned to word boundary, dst aligned to double word boundary.
- Src aligned to 16 bit boundary, dst aligned to word boundary.
- Src aligned to word boundary, dst aligned to 16 byte boundary.
- Src aligned to word boundary, dst aligned to 1 byte from a word
  boundary.
- Src aligned to word boundary, dst aligned to 2 bytes from a word
  boundary.
- Src aligned to word boundary, dst aligned to 3 bytes from a word
  boundary.
- Src aligned to 1 byte from a word boundary, dst aligned to a word
  boundary.
- Src aligned to 2 bytes from a word boundary, dst aligned to a word
  boundary.
- Src aligned to 3 bytes from a word boundary, dst aligned to a word
  boundary.

Cases to verify the unaligned source code properly aligns to a 16 bit
boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  4 + 128 bit boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  8 + 128 bit boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  12 + 128 bit boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  16 + 128 bit boundary.

In all cases, a two byte fencepost was placed at the end of the
destination to verify that only the requested number of bytes were copied.

Bug: 8005082

Merge from internal master.

(cherry-picked from commit 21ede92d794969f22cacbdb9f557818f1c5712b5)

Change-Id: Ief70c9e6dc8c6473ae245b6570b2c266fed9618c
Add missing branch in memcpy.S dst aligned case.

Merge from internal master.

(cherry-picked from commit 6ffaa931c362602a2b606a610c92326a425a876e)

Change-Id: Ifdcf01fd122866cf0d4c5b5f7a997803561d7889
Rewrite memset for cortexa15 to use strd.

Merge from internal master.

(cherry-picked from commit 7ffad9c120054eedebd5f56f8bed01144e93eafa)

Change-Id: Ia67f2a545399f4fa37b63d5634a3565e4f5482f9
Remove redundant space within square brackets

The new "as" in binutils-2.23 (with gcc4.8) is more picky:
it expects register right after [

Change-Id: I876124841582070ab2083ffafe38bc333b5812d0
Fix assembler errors in generic arm strlen.c.

Tested using a static version of the strlen libc_test program
on a nexus7 that uses the generic code.

Merge from internal master.

(cherry-picked from d8d10a8994472e40d19301b7087806630877b4d5)

Change-Id: I88f7dc01dc5b5c3ac2d5580d92153bc1bc36c564
libgcc_compat: Introduce __aeabi_lasr for cortex-a9 and higher

This is needed when passing -mcpu=cortex-a9 or higher on a modern
toolchain for prebuilt library compatibility

Change-Id: I73eb2393377914ae26216a8c2828ad973d1c1225
linker: restore prelink support

Prelink support is required to load old vendor binary blobs
on many devices properly

This commit partially reverts 4688279db5dcc4004941e7f133c4a1c3617d842c

Change-Id: Iee5325e048daee78e8dcaa47c87454b908c89b4e