fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
fhdl/structure: store clock domain name
flow/perftools: finish removing ActorNode
sim: default runner to Icarus Verilog
doc: update to new Migen APIs
doc: do not inline examples as this never works with most Sphinx setups ...
doc: multiple clock domains
doc/dataflow: remove ALA
doc/dataflow: remove ActorNode
Merge branch 'master' of github.com:milkymist/migen
doc: fix signal desc layout
fhdl/autofragment: from_attributes
fhdl: tristate support
Merge branch 'master' of git://github.com/milkymist/migen
- Wip fifos / domain_crossing