Don't turn Vec into ROM unless width is known
Don't include Literals in VCD
Fix swapped definitions of (UFix / Fix) and (UFix % Fix)
Don't fold signed operators

The folding code is only correct for unsigned operations.
For C++, specify mul/div destination width

This allows the destination width to be set independently of the input widths.
Implement signed-by-unsigned mul/div in terms of signed-signed mul/div

Verilog doesn't natively support these operations directly, so we were generating incorrect code.
Added asDirectionless method. Used to strip directions from intra-component FIFOIO wires, i.e. a workaround for component stack weirdness with bundle parenting
cleaned up detection of user code, made recompatible with nodes outside of components
fix test regressions
rename abstract AtomData to abstract Bits to simplify branch merge
Rework the hierarchy derived from class Data

* Bits becomes an abstract class.
* object Bits is a pass-through for object UFix and has been marked deprecated.
* Bool is a subclass of UFix.
* extracting a single bit out of a Bits instance will return a Bool.
merge after patched ucb-bar/chisel for rework of Data class hierarchy