KVM: ARM-VGIC: Support KVM_CREATE_DEVICE for VGIC

Support creating the ARM VGIC device through the KVM_CREATE_DEVICE
ioctl, which can then later be leveraged to use the
KVM_{GET/SET}_DEVICE_ATTR, which is useful both for setting addresses in
a more generic API than the ARM-specific one and is useful for
save/restore of VGIC state.

Adds KVM_CAP_DEVICE_CTRL to ARM capabilities.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
KVM: ARM-VGIC: Set base addr through device API

Support setting the distributor and cpu interface base addresses in the
VM physical address space through the KVM_{SET,GET}_DEVICE_ATTR API
in addition the ARM specific API.

This has the added benefit of being able to share more code in user
space and do things in a uniform maner.

Also deprecate the older API at the same time, but backwards
compatibility will be maintained.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
irqchip: Define additional MMIO offsets and masks

Define CPU interface offsets for the GICC_ABPR, GICC_APR, and GICC_IIDR
registers.  Define distributor registers for the GICD_SPENDSGIR and the
GICD_CPENDSGIR.  KVM/ARM needs to know about these definitions to fully
support save/restore of the VGIC.

Also define some masks and shifts for the various GICH_VMCR fields.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
KVM: arm-vgic: Make vgic mmio functions more generic

Rename the vgic_ranges array to vgic_dist_ranges to be more specific and
to prepare for handling CPU interface register access as well (for
save/restore of VGIC state).

Pass offset from distributor or interface MMIO base to
find_matching_range function instead of the physical address of the
access in the VM memory map.  This allows other callers unaware of the
VM specifics, but with generic VGIC knowledge to reuse the function.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
KVM: arm-vgic: Add vgic reg access from dev attr

Adds infrastructure to handle distributor and cpu interface register
accesses through the KVM_{GET/SET}_DEVICE_ATTR interface by adding the
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS groups
and defining the semantics of the attr field to be the MMIO offset as
specified in the GICv2 specs.

This does not actually implement missing register accesses to let the
full VGIC state be accessible from user space, nor does it handle
potential situations where the existing handle_mmio functions are not
handling a save/restore scenario well enough, that will come in the
following patches.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers

Handle MMIO accesses to the two registers which should support both the
case where the VMs want to read/write either of these registers and the
case where user space reads/writes these registers to do save/restore of
the VGIC state.

Note that the added complexity compared to simple set/clear enable
registers stems from the bookkeping of source cpu ids.  It may be
possible to change the underlying data structure to simplify the
complexity, but since this is not in the critical path, at all, this is
left as an interesting excercise to the reader.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
KVM: arm-gic: Support user-space CPU int. register access

Implement support for the CPU interface register access from user space
to support save/restore of VGIC state.

This commit supports the same logic as the current VGIC support.  For
example, the active priority registers are handled as RAZ/WI.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>