VHDL LUTs correctly initialized (Verification on whether or not the binary has to be reversed still needed)
xor example with consts test
flipflop test
xst synthesis test fix
Changes to VHDL priting, latch inputs can now be inverted and inputs can be connected directly to the output.
vhdl generation code cleanup
cleanup and debugging VHDL generation
bugfix for LUTs with inverted_LUT inputs
bugfix duplicated TLUTs (inverted and regular)
rom example
Fixed input inversion in LUT VHDL printing
added possibility to build java tools using ant
support for correctly initialised LUTs, removing the need to reconfigure them: fix the c evaluation function
Merge bugfix into mixec_circuit
rom example on XUPV5
quiet testing
remove need to manually copy abc.rc
code cleanup, extra check on quartus output
rom example added to testsuite
throw exceptions when problems occur instead of printing error and exiting