clk: Always notify whole subtree when reparenting

A clock's notifier count only reflects notifiers which are registered
directly for that clock. A reparent operation though affects the whole
subtree because of a potential rate change.
When issuing the pre rate change notifications only the notifier count
for the clock to be changed is considered and notifiers for subclocks
may never be called. Resulting in clocks in the subtree which have
registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE
notification, without a PRE_RATE_CHANGE_NOTIFICATION.
Therefore always traverse the whole subtree when issueing pre rate
change notifications during a reparent operation.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
(cherry picked from commit f3aab5d61400b794ec759b9345e93e7ba57eb369)
i2c: xi2cps: Don't obstruct rate changes if suspended

When the driver is suspended its input frequency doesn't matter and
changes to it should not be prevented.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clk: zynq: Add clock controller driver

Add a clock controller driver and documentation.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clk: zynq: Factor out PLL driver

Refactor the PLL driver so it works with the clock controller driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
v2:
 - use #defines for FBDIV min and max values
 - fix documentation for pll register function
arm: zynq: Migrate to clock controller

Switch Zynq, including its drivers, over to use the new clock
controller. And remove old clock implementation.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
v2:
 - add 'clocks' property to DMA nodes in DT
 - migrate the zc702-TRD dts file
clk/zynq/clkc: Add 'fclk-enable' functionality

In cases no proper drivers are avaiable and enabling the FCLKs through
the CCF and activation through userspace is not an option either, the
clkc needs a way to enable the FCLKs.

A new property - 'fclk-enable' - is added to the DT bindings. It's value
is a bitmask, where a set bit results in enabling the corresponding FCLK
through the clkc.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: zynq: Set proper GIC flags

Zynq is able to wake up on any IRQ, so flag it with
IRQCHIP_SKIP_SET_WAKE, and we want to mask off the IRQs when
going to suspend to avoid transient effects so also flag
this with IRQCHIP_MASK_ON_SUSPEND.

This is essentially, making the same changes as commit
'ARM: ux500: set proper GIC flags'
(sha1: 7e1f97ea8ffa66679252520dbbbd6ec413ecae68) for Zynq.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
cpufreq: zynq: Support suspend

Add a check to prevent changes to the clock dividers while PLLs are
bypassed.
Without this check, cpufreq may set a minimum divider for the CPU clock
based on the very low frequency during PLL bypass. This results in
exceeding all limits for the CPU frequency when the original PLL
frequency is restored during resume.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
tty: xuartps: Update suspend/resume code

This update allows the UART input frequency to change during a suspend
cycle. This way PLLs can be bypassed even while the UART is the active
wake up device.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clk: Introduce 'clk_round_rate_nearest()'

Introduce a new API function to round a rate to the closest possible
rate the HW clock can generate.
In contrast to 'clk_round_rate()' which works similar, but always returns
a frequency <= its input rate.

The function code was sent to LKML by Uwe Kleine-König
<u.kleine-koenig@pengutronix.de>.

Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
arm: zynq: Change OPP calculation

When the frequencies given in OPPs are converted to a frequency table
for the cpufreq driver, we lose three magnitudes of resolution, since
the CCF works with Hz and cpufreq with kHz frequencies.
Leverage the new 'clk_round_rate_nearest()' API function to calculate
OPP frequencies which should result in the intended actual frequency.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
can: xilinx: Added xilinx can controller driver support

Added xilinx can controller driver support

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
i2c: xilinx: Fix compilation error

It was reported by zero day testing system

Bug was introduced by this commit:
"i2c: xilinx: Fix i2c sparse warnings"
(sha1: 4b21ab8d8eb1fb64a1f46833db436b2c3cea21cf)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
GPIO: xilinxps: Enable GENERIC_IRQ_CHIP in Kconfig

It is required by the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
GPIO: xilinx: Use standard coding style for macros

Trivial.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
GPIO: xilinx: Fix kernel-doc mainline

Fix kernel-doc format in the whole driver not to report
any warning.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
GPIO: xilinx: Add irq support to the driver

Only rising edge is supported.
Allocate irq chip per channel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
rpmgs: Fix problem with not synchronized cache_table

Cached resource table is copied over loaded one
in the start but changed loaded one is not copied
over cached one which is used in virtio removal
where status property must be zero.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
rpmsg: freertos: Support more instances of rpmgs driver

Support concurent ARM and Microblaze instances.
Optionally more than 1 Microblaze instance.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
remoteproc: zynq: Do not call rproc_put() when rproc_alloc() failed

rproc_put should be called when rproc_add failed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>