Change how to get cacheline size

Some architecture does not support getting of LEVEL1_DCACHE_LINESIZE
by getconf. For example, ARM will return 0. Therefore, this can not be
built by architecture that is not supported LEVEL1_DCACHE_LINESIZE.
As far as I checked, 32bit architecture such as ARM, MIPS and other align
with 32.

This changes that set 32 to CACHELINE_SIZE when the LEVEL1_DCACHE_LINESIZE
returns 0. It is difficult to cope in all architecture, but this can support
much architectures.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Change CPUFLAGS to -march=native

Currently CPUFLAGS is set "-March = core2-mtune = corei7". We can not
be built by non-Intel 64bit architecture.
This patch sets the "-march = native" to CPUFLAGS. we will be able to
build many architectures by this.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>