msm: clock-7x30: Make mdp_vsync_clk source explicit

The mdp_vsync_clk's frequency table has its source as SRC_MAX
when the clock is really sourcing off of LPXO. Fix it to be more
explicit about which source is actually being used.

Change-Id: Ief92da1645524b507e86adb617d08d2f83fcac1b
Signed-off-by: Stephen Boyd <sboyd@quicinc.com>
msm_fb: Fix mdp_lcdc_pclk_clk clock rate on 8x50

On 8x50 proc_comm doesn't round the mdp_lcdc_pclk_clk rate.
Therefore, set the rate to the one expected by 8x50 and assume it
will be rounded correctly on 7k targets.

Change-Id: Ibcf1934c89df12cf00eeda1d6ca27ea7bb6d8ac6
Signed-off-by: Stephen Boyd <sboyd@quicinc.com>