fix insn using src1 port - new field coding types

Add two new field coding types in order to encode separately the msb and lsb
of a register pair.

This will be needed to encode some opcodes the same way as Ti assembler does
with instructions that use src1 port of DSP to load the LSB of a double-
precision operand value.

Corresponding instructions are: absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp.
See SPRUFE8B.pdf p. 105, 258, 260, 262 and 418.
fix insn using src1 port - gas support

For absdp, dpint, dpsp, dptrunc, rcpdp and rsqrdp instructions, Ti's SDK
assembler encodes individual register numbers of the reg pair into
src1 (even register / LSB) and src2 (odd register / MSB).

Don't know if this is mandatory as it contradicts Ti's own documentation
of the corresponding opcode and any value in the src1 field yields
the same output with Ti SDK disassembler and that seems contradictory
with the opcode definitions (src1 = 00000b).

Add proper infrastructure that will enable binutils to generate the same
opcodes as Ti's assembler does.
fix insn using src1 port - libopcode support

For absdp, dpint, dpsp, dptrunc, rcpdp and rsqrdp instructions, Ti's SDK
assembler encodes individual register numbers of the reg pair into
src1 (even register / LSB) and src2 (odd register / MSB).

Decodes the reg pair using individual msb and lsb halves but discard the
src1 (lsb) value and only use the src2 (msb) to follow what Ti SDK does
as any value in the src1 field yields the same output with SDK disassembler.
fix insn using src1 port - absdp instruction

Fix absdp opcode generation and disassembling :
 - modify absdp opcode table entry to use dreg_msb and greg_lsb field coding
 - modify existing test case to expect msb reg in src2 and lsb reg in src1
   in gas-generated absdp opcode (like Ti assembler does)
 - add a test case to allow any value in src1 in libopcode ans still output
   correct instruction  disassembly (like Ti disassembler does)
fix insn using src1 port - dpint instruction

Fix dpint opcode generation and disassembling :
- modify absdp opcode table entry to use dreg_msb and greg_lsb field coding
- modify existing test case to expect msb reg in src2 and lsb reg in src1
in gas-generated absdp opcode (like Ti assembler does)
- add a test case to allow any value in src1 in libopcode ans still output
correct instruction disassembly (like Ti disassembler does)
fix insn using src1 port - dpsp instruction

Fix dpsp opcode generation and disassembling :
- modify absdp opcode table entry to use dreg_msb and greg_lsb field coding
- modify existing test case to expect msb reg in src2 and lsb reg in src1
in gas-generated absdp opcode (like Ti assembler does)
- add a test case to allow any value in src1 in libopcode ans still output
correct instruction disassembly (like Ti disassembler does)
fix insn using src1 port - dptrunc instruction

Fix dptrunc opcode generation and disassembling :
- modify absdp opcode table entry to use dreg_msb and greg_lsb field coding
- modify existing test case to expect msb reg in src2 and lsb reg in src1
in gas-generated absdp opcode (like Ti assembler does)
- add a test case to allow any value in src1 in libopcode ans still output
correct instruction disassembly (like Ti disassembler does)
fix insn using src1 port - rcpdp instruction

Fix rcpdp opcode generation and disassembling :
- modify absdp opcode table entry to use dreg_msb and greg_lsb field coding
- modify existing test case to expect msb reg in src2 and lsb reg in src1
in gas-generated absdp opcode (like Ti assembler does)
- add a test case to allow any value in src1 in libopcode ans still output
correct instruction disassembly (like Ti disassembler does)
fix insn using src1 port - rsqrdp instruction

Fix rsqrdp opcode generation and disassembling :
- modify absdp opcode table entry to use dreg_msb and greg_lsb field coding
- modify existing test case to expect msb reg in src2 and lsb reg in src1
in gas-generated absdp opcode (like Ti assembler does)
- add a test case to allow any value in src1 in libopcode ans still output
correct instruction disassembly (like Ti disassembler does)
fix insn using src1 port - simplify disassembly

After carefull cross checking :

Ti disassembler :
 - only bits 0-4 of src2 field is used to encode the regpair

Ti assembler :
 - encodes msb of regpair in src2 and lsb of regpair in src1

With this commit, binutils will do exactly the same.
fix insn using src1 port - keep testing old opcodes
fix insn using src1 port - remove debug message