ARM: SMP: use a timing out completion for cpu hotplug
	modified:   arch/arm/kernel/smp.c
ARM: 7011/1: Add ARM cpu topology definition

The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

(cherry-picked from i9100 kernel)
ARM: 7182/1: ARM cpu topology: fix warning

kernel/sched.c:7354:2: warning: initialization from incompatible pointer type

Align cpu_coregroup_mask prototype interface with sched_domain_mask_f typedef
use int cpu instead of unsigned int cpu

Cc: <stable@vger.kernel.org>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
sched: Ensure cpu_power periodic update

With a lot of small tasks, the softirq sched is nearly never called
when no_hz is enabled. In this case load_balance() is mainly called
with the newly_idle mode which doesn't update the cpu_power.

Add a next_update field which ensure a maximum update period when
there is short activity.

Having stale cpu_power information can skew the load-balancing
decisions, this is cured by the guaranteed update.

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1323717668-2143-1-git-send-email-vincent.guittot@linaro.org
ARM: cpu topology: Enable ARCH_POWER

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
ARM: topology: save cpu id of each core
ARM: topology: Update topology according to current sched_mc mode
ARM: topology: Add a cpu_power function
ARM: topology: Add a topology update notification
ARM: cpu topology: Add asym topology flag for using cpu0 1st

Modify the CPU sched_domain flags in powersave mode for using the cpu0 in ched_mc powersave mode

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
ARM: cpu topology: add debugfs
cpupower: update the cpu_power according to cpu load

This driver updates the capacity of each core according to current
sched_mc level and cpu frequency (in fact current cpu load)

When the lowest frequencies are used, we are in a light load use case
and we increase the cpu capacity to keep these light tasks on CPU0

Conflicts:

	drivers/staging/Kconfig
IOSCHED: Add BFQ IO-Scheduler
  * prepare Kernel Tree for BFQ
  * Add BFQ IO-Sched

Conflicts:
	block/Kconfig.iosched
	block/Makefile
CPU GOV Force SYNC:

Force Settings applied to one core (freq changes etc) to apply on second core also
 * can be enabled/disabled vis SYSFS

Conflicts:
	drivers/cpufreq/Kconfig
	drivers/cpufreq/cpufreq.c
MPDEC: update msm_mpdec

Conflicts:
	arch/arm/mach-msm/msm_mpdecision.c
jakeday a year ago disable fsync (makes data writes quicker and better on battery)
markus-oberhumer a month ago lib/lzo: huge LZO decompression speedup on ARM by using unaligned access
Updated IO Stats
	modified:   block/deadline-iosched.c
	modified:   kernel/sched_fair.c
Increased MIN_READAHEAD

Conflicts:
	include/linux/mm.h
from 3.x: sched/rt: Improve pick_next_highest_task_rt() Quarx2k