i965: Remove GL_ARB_color_buffer_float from GL core contexts.

Of the 3 controls in the extension, one was kept in GL core and the other
two were explicitly deprecated and the reasonable default behavior was
encoded in the spec.  By not exposing the extension, we avoid shader
recompiles when switching between float and unorm color buffers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
radeon/llvm: Don't use the global context when parsing LLVM IR

This leads to crashes when multiple threads try to compile compute
shaders in the same time.

Fixes a crash in bfgminer when using more than one thread.
gallivm: Move LLVMStartMultithreaded() static initializer into gallivm

This does not solve all of the problems with using LLVM in a
multithreaded enivronment, but it should help in some cases.

Reviewed-by: Mathias.Froehlich@web.de
radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2

The LLVM C API is considered stable and should never change, so it
is much more desirable to use than the LLVM C++ API, which is constantly in
flux.

v2:
  - Split target initialization and lookup into separate functions

Reviewed-by: Mathias.Froehlich@web.de
radeon/llvm: Always build libradeonllvm as static

This library is very small, so there is not much to gain from building
it as a shared library.  Also, when linking statically with LLVM, a
shared libradeonllvm exports LLVM symbols and creates problems when
used with other shared objects that also link statically to LLVM.

Reviewed-by: Mathias.Froehlich@web.de
mesa: Add infrastructure for ARB_gpu_shader5.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
glsl: Rework ir_reader to handle expressions with four operands.

Needed to support the bitfieldInsert() built-in added by
ARB_gpu_shader5.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
glsl: Add support for new bit built-ins in ARB_gpu_shader5.

v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
glsl: Add constant evaluation of bit built-ins.

v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
v3: Add ir_triop_bitfield_extract as an exception to the op[0]->type ==
    op[1]->type assertion in ir_constant_expression.cpp.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
glsl: Add a pass to lower bitfield-insert into bfm+bfi.

i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.

v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp.
    Remove spurious temporary assignment and dereference.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add Gen7+ fields to brw_instruction and add comments.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add 3-src destination and shared-source type macros.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/gen7: Set src/dst types for 3-src instructions.

Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.

v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well.
    Assert that src2.type (instead of src0.type) matches dest.type since
    it's the primary argument and src0 and src1 might correctly have
    different types.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
i965: Print the correct dst and shared-src types for 3-src instructions.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add support for emitting and disassembling bit instructions.

Specifically
   bfe - for bitfieldExtract()
   bfi1 and bfi2 - for bitfieldInsert()
   bfrev - for bitfieldReverse()
   cbit - for bitCount()
   fbh - for findMSB()
   fbl - for findLSB()

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965/fs: Add support for bit instructions.

Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.

v2: Subtract result of FBH from 31 (unless an error) to convert
    MSB counts to LSB counts.
v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref
    channel_expressions) from appearing multiple times in the IR.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
i965/vs: Add support for bit instructions.

v2: Rebase on LRP addition.
    Use fix_3src_operand() when emitting BFE and BFI2.
    Add BFE and BFI2 to is_3src_inst check in
      brw_vec4_copy_propagation.cpp.
    Subtract result of FBH from 31 (unless an error) to convert
      MSB counts to LSB counts

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Lower bitfieldInsert.

v2: Only lower bitfieldInsert to BFM+BFI (and don't lower
    bitfieldExtract at all) since three-source instructions are now
    usable in the vertex shader.
v3: Lower bitfield_insert in the same pass with everything else, since
    it doesn't produce any instructions to be lowered (the other two
    lowering passes that were in a previous iteration of this series
    emitted subtractions which needed to be lowered).

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
r600g/llvm: Don't emit CALL_FS for vertex shaders

The LLVM backend takes care of this now.