Project: Integrate SHA1 core into User Logic

This commit introduces a very simply FSM to connect the pcore register interface
to the SHA1 core engine.  I also created a simple test case to verify this FSM
works.

That said it's still missing the following functionality:

1. The user currently has to clear the register 0 or else the FSM will
immediately start another round of hashing.

2. We need to provide a mechanism for the user to start a new block.

3. The code could be cleaned up a bit.  It's rather verbose as it currently
stands and there are several unused signals cluttering up the file.

I elected NOT to include the project file changes since the paths will likely be
different, hence just the VHDL files are included in this commit.