Reformat slightly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189630 91177308-0d34-0410-b5e6-96231b3b80d8
Don't bother emitting the pubtypes section on darwin since there aren't
any maintained consumers of it on that platform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189631 91177308-0d34-0410-b5e6-96231b3b80d8
Random cleanup: No need to use a std::vector here, since createInternalizePass uses an ArrayRef.

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comment typo

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[PowerPC] Add loads, stores, and related things to fast-isel.

This is the next big chunk of fast-isel code.  The primary purpose is
to implement selection of loads and stores, but there is a lot of
drag-along to support this.  The common code to analyze addresses for
both loads and stores is substantial.  It's also necessary to add the
materialization code for global values.

Related to load-store processing is the code to fold loads into
integer extends, since otherwise we generate lots of redundant
instructions.  We also need to add some overrides to some FastEmit
routines to ensure we don't assign GPR 0 to a virtual register when
this would change the meaning of an instruction.

I added handling selection of a few binary arithmetic instructions, to
enable committing some test cases I wrote a while back.

Finally, ap couple of miscellaneous changes:
 * I cleaned up some poor style from a previous patch in
   PPCISelLowering.cpp, pointed out by David Blaikie.
 * I enlarged the Addr.Offset field to avoid sign problems with 32-bit
   offsets. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189636 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Miscellaneous fast-isel test cases.

Here are a few more tests that now pass after the recent fast-isel
commits.


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Remove bogus debug statement.  Sheesh.

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[PowerPC] Handle selection of compare instructions in fast-isel.

Mostly trivial patch adding support for compares.  The meat of the
work was added with the branch support.


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mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.

Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.

Added a getUpwardPressureDelta API that will soon replace the old
one. Compute PressureDelta here from the precomputed PressureDiffs.

Updating for liveness will come next.

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 mi-sched: improve the generic register pressure comparison.

Only compare pressure within the same set. When multiple sets are
affected, we prioritize the most constrained set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189641 91177308-0d34-0410-b5e6-96231b3b80d8
Replace LiveInterval::killedAt with isKilledAtInstr.

Return true for LRGs that end at EarlyClobber or Register slots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189642 91177308-0d34-0410-b5e6-96231b3b80d8
mi-sched: update PressureDiffs on-the-fly for liveness.

This removes all expensive pressure tracking logic from the scheduling
critical path of node comparison.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189643 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "ARM: Improve pattern for isel mul of vector by scalar."

This reverts commit r189619.

The commit was breaking the arm_neon_intrinsic test.

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Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, Y), -1)). Fixes PR17038.

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Remove unused X86andn_flag node.

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Fixup BZHI selection to remove an unneeded zero extension.

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Restore llvm-ranlib expansion in RUN-lines removed in r184019

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X86: Add a description of the Intel Atom Silvermont CPU.

Currently this is just the atom model with SSE4.2 enabled.

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InstCombine: Check for zero shift amounts before subtracting one causing integer overflow.

PR17026. Also avoid undefined shifts and shift amounts larger than 64 bits
(those are always undef because we can't represent integer types that large).

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Checking commit access; removed one space added in previous test checkin by Jim

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