[DRIVERS] block: Fix compile error in rbd driver

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_devtree: Add CPU node attributes for DTB-based SMP core bringup

Going forward we would like to have ful DTB-based secondary core bringup
for SMP host. This means our architecture specific code would get info
required for bringup secondary cores from CPU nodes under /cpus.

Signed-off-by: Anup Patel <anup@brainfault.org>
[LIBS] Add ELF machine type for Aarch64

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Sukanto Ghosh <sukantoghosh@gmail.com>
[ARM] Add feature and cpuid for generic ARMv8 VCPU

Upcoming arm64 port would require us to distinguish between
ARMv7 VCPUs and ARMv8 VCPUs hence adding ARM_FEATURE_V8 and
ARM_CPUID_ARMV8 for a generic ARMv8 VCPU in-advance.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Sukanto Ghosh <sukantoghosh@gmail.com>
[ARM] arm32ve: Fix prototype of arch_vcpu_regs_dump()

The prototype of arch_vcpu_regs_dump() has changed and now it
takes pointer to character device (on which printing is to be
done) as argument.

This patch fixes arm32ve implementation of arch_vcpu_regs_dump().

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARCH] Replace atomic testnset operation with cmpxchg operation

The atomic compare-and-exchange operation always returns
previous value of the atomic variable. If the returned
previous value is same as expected compare value (or old
value) then operation succeed else it failed.

As per above, we can easily express atomic test-and-set
operation in-terms of atomic compare-and-exchange operation
hence atomic compare-and-exchange is more generic.

This patch replaces arch specific test-and-set operation with
arch specific compare-and-exchange operation so that derive
more atomic operations using atomic compare-and-exchange.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_vcpu_irq: refactor a bit of code

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[ARM] mmu_lpae: Use lite version of spin lock APIs

To avoid dependency on vmm_scheduler_preempt_xxx() APIs and to
improve things a bit we use lite version of spin lock APIs in
MMU LPAE.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_host_ram: Use lite version of spin lock APIs

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_host_vapool: Use lite version of spin lock APIs

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] mmu_lpae: Make _setup_initial_ttbl() suitable for both arm32ve and arm64

The aarch64 compiler treats "&a" as address of global variable "a"
relative to current PC. In other words, "&a" for global variable "a"
mean PC + relative offset of "a". This way of treating "&a" is good
but breaks _setup_intial_ttbl() which assumes that "&a" is link time
absolute address of global variable "a".

This patch fixes above described issue in _setup_initial_ttbl() so
that it is suitable for both arm32ve and arm64.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Sukanto Ghosh <sukantoghosh@gmail.com>
Merge remote branch 'upstream/master'
[ARM] unify ARM32 and ARM32VE lock implementation.

Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>
[EMULATORS] virtio_console: Minor fix for read operation on emerg_wr

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Add config option for selecting common locking implementation

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_vcpu_irq: Fix vmm_vcpu_irq_deassert() semantics

The patch "[CORE] vmm_vcpu_irq.c: refactor a bit the code" changed
vmm_vcpu_irq_deassert() and forece vcpu irq deassert request to be
ordered after vcpu irq assert request. In other words, we can only
deassert vcpu irq if it was asserted previously else dessert request
is ignored.

In case of ARM32VE (or any architecture that supports vcpu irq assert
and vcpu irq deassert), it is not mandatory that vcpu irq deassert
will always follow vcpu irq assert. The ordering of vcpu irq assert
and vcpu irq deassert is architecture dependent. In case of ARM32VE,
the generic timer code induces a vcpu irq deassert before vcpu irq
assert via GIC emulator to route HW virtual timer irq to VCPU.

This patch again makes vcpu irq assert and vcpu irq deassert
unordered.

Signed-off-by: Anup Patel <anup@brainfault.org>
[LIBS] Add API to clear or empty the FIFO

Signed-off-by: Anup Patel <anup@brainfault.org>
[EMULATORS] virtio_console: Clear emerg_rd fifo upon reset

The emerg_rd fifo of virtio_console is always capturing Rx data
hence we need to clear previous content when virtio_console
device is reset.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] vmm_guest_aspace: Fix is_region_overlapping() for adjacent regions

If we have two regions A and B adjacent to each other in guest physical
address space then is_region_overlapping() will fail if device tree node
for region B is before region A under guest aspace node.

This patch fixes above described issue in is_region_overlapping().

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Fix usage of mmu_lpae_map_page() in cpu_vcpu_stage2_map()

Lets say we have SMP Guest with 2 VCPUs running on SMP Host.
Now if the VCPUs are scheduled on different host CPUs then
we hit a potential race condition where both VCPUs get Stage2
abort simultaneously accessing same Guest region. If we hit
this race condition then the call to mmu_lpae_map_page() from
cpu_vcpu_stage2_map() will fail for one of the VCPUs.

The issue will manifest for SMP Guest running on SMP host only
because we share same Stage2 ttbl for all VCPUs of SMP Guest
and we assume that mmu_lpae_map_page() will always succeed when
called from cpu_vcpu_stage2_map().

This patch fixes this issue by re-checking if Stage2 page is
already mapped when mmu_lpae_map_page() fails.

Reported-by: Po-wen Cheng <sting.cheng@gmail.com>
Signed-off-by: Anup Patel <anup@brainfault.org>