tcg-ppc: fix qemu_ld/qemu_st for AIX ABI

For the AIX ABI, the function pointer and small area pointer need
to be loaded in the trampoline.  The trampoline instead is called
with a normal BL instruction.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: use new return-argument ld/st helpers

These use a 32-bit load-of-immediate to save a mflr+addi+mtlr sequence.
Tested with a Windows 98 guest (pretty much the most recent thing I
could run on my PPC machine) and kvm-unit-tests's sieve.flat.  The
speed up for sieve.flat is as high as 10% for qemu-system-i386, 25%
(no kidding) for qemu-system-x86_64 on my PowerBook G4.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Avoid code for nop move

While these are rare from code that's been through the optimizer,
it's not uncommon within the tcg backend.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Cleanup tcg_out_qemu_ld/st_slow_path

Coding style fixes.  Use TCGReg enumeration values instead of raw
numbers.  Don't needlessly pull the whole TCGLabelQemuLdst struct
into local variables.  Less conditional compilation.

No functional changes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Use conditional branch and link to slow path

Saves one insn per slow path.  Note that we can no longer use
a tail call into the store helper.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc: Fix and cleanup tcg_out_tlb_check

The fix is that sparc has so many mmu modes that the last one overflowed
the 16-bit signed offset we assumed would fit.  Handle this, and check
the new assumption at compile time.

Load the tlb addend earlier for the fast path.

Remove the explicit address + addend and make use of index addressing.

Adjust constraints for qemu_ld64 such that we don't clobber the address
register or tlb addend before loading both values.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Reformat tcg-target.c

Whitespace and brace changes only.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: More use of TAI and SAI helper macros

Finish conversion of all memory operations.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use TCG_REG_Rn constants

Instead of bare N, for clarity.  The only (intentional) exception made
is for insns that encode R|0, i.e. when R0 encoded into the insn is
interpreted as zero not the contents of the register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use tcg_out64

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Avoid code for nop move

While these are rare from code that's been through the optimizer,
it's not uncommon within the tcg backend.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Don't load the static chain from TCG

There are no helpers that require the static chain.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Fold constant call address into descriptor load

Eliminates one insn per call:

 :  lis     r2,4165
-:  ori     r2,r2,59616
-:  ld      r0,0(r2)
+:  ld      r0,-5920(r2)
 :  mtctr   r0
-:  ld      r2,8(r2)
+:  ld      r2,-5912(r2)
 :  bctrl

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Look through a constant function descriptor

Especially in the user-only configurations, a direct branch into
the executable may be in range.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Tidy register allocation order

Remove conditionalization from tcg_target_reg_alloc_order, relying on
reserved_regs to prevent register allocation that shouldn't happen.
So R11 is now present in reg_alloc_order for __APPLE__, but also now
reserved.

Sort reg_alloc_order into call-saved, call-clobbered, and parameters.
This reduces the effect of values getting spilled and reloaded before
function calls.

Whether or not it is reserved, R2 (TOC) is always call-clobbered.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Handle long offsets better

Previously we'd only handle 16-bit offsets from memory operand without falling
back to indexed, but it's easy to use ADDIS to handle full 32-bit offsets.

This also lets us unify code that existed inline in tcg_out_op for handling
addition of large constants.

The new R2 temporary was marked reserved for the AIX calling convention, but
the register really is call-clobbered and since tcg generated code has no use
for a TOC, it's available for use.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement tcg_register_jit

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Streamline tcg_out_tlb_read

Less conditional compilation.  Merge an add insn with the indexed
memory load insn.  Load the tlb addend earlier.  Avoid the address
update memory form.

Fix a bug in not allowing large enough tlb offsets for some guests.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Add _noaddr functions for emitting forward branches

... rather than open-coding this stuff through the file.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement CONFIG_QEMU_LDST_OPTIMIZATION

Signed-off-by: Richard Henderson <rth@twiddle.net>