i965: Fix typo in doxygen hyperlink

s/brw_state_upload/brw_upload_state/

Found because the link was broken.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
gallivm: clean up passing derivatives around

Previously, the derivatives were calculated and passed in a packed form
to the sample code (for implicit derivatives, explicit derivatives were
packed to the same format).
There's several reasons why this wasn't such a good idea:
1) the derivatives may not even be needed (not as bad as it sounds since
llvm will just throw the calculations needed for them away but still)
2) the special packing format really shouldn't be part of the sampler
interface
3) depending what the sample code actually does the derivatives will
be processed differently, hence there is no "ideal" packing. For cube
maps with explicit derivatives (which we don't do yet) for instance the
packing looked downright useless, and for non-isotropic filtering we'd
need different calculations too.

So, instead just pass the derivatives as is (for explicit derivatives),
or let the rho calculating sample code calculate them itself. This still
does exactly the same packing stuff for implicit derivatives for now,
though explicit ones are handled in a more straightforward manner (quick
estimates show performance should be quite similar, though it is much
easier to follow and also does the rho calculation per-pixel until the
end, which we eventually need for spec compliance anyway).

No piglit changes.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
nv50: Remove nv0_ir_from_sm4.*

Unused, depends on d3d1x.

Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>
d3d1x: Remove.

Unused/unmaintained.

Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>
freedreno: gallium driver for adreno

Currently works on a220.  Others in the a2xx family look pretty similar
and should be pretty straightforward to support with the same driver.

The a3xx has a new shader ISA, and while many registers appear similar,
the register addresses have been completely shuffled around.  I am not
sure yet whether it is best to support with the same driver, but
different compiler, or whether it should be split into a different
driver.

v1: original
v2: build file updates from review comments, and remove GPL licensed
    header files from msm kernel
v3: smarter temp/pred register assignment, fix clear and depth/stencil
    format issues, resource_transfer fixes, scissor fixes

Signed-off-by: Rob Clark <robdclark@gmail.com>
mesa: Use correct functions for enum conversion.

Fixes mixing enum types defects reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
nouveau: Bail out from nouveau_fence_wait if flushing the pushbuf fails.
nv50/ir: Clean up references to function values before destroying them.
nv50/ir/opt: Fix tryPropagateBranch for BBs with several exit branches.

Comments and "if (bf->cfg.incidentCount() == 1)" condition added
by Christoph Bumiller.
nv50/ir/ra: Fix argument const-ness in RegisterSet::idToUnits and idToBytes
nv50/ir/ra: Fix RegisterSet::occupy(const Value *v).
nv50/ir/ra: Fix traversal before the beginning of the active list in buildRIG.
nv50/ir/ra: Fix maxGPR calculation for programs with multiple functions.
nv50/ir/ra: swap copyCompound args if src is compound and dst isn't
nv50/ir/ra: fix confusion with conditional RegisterSet::occupy
nv50/ir/ra: also add pre-existing MERGE,SPLIT to constraint list
nv50/ir/ra: make sure all used function inputs get assigned a reg

A live range [0, 0) counts as empty. For function inputs this can
be a problem, so insert a nop at the beginning to make it [0, 1).
This is a bit of a hack but also the most simple solution.
nv50/ir/tgsi: Accept COMPUTE programs.
nv50/ir/tgsi: Translate grid-related system parameters.
nv50/ir: fix comparison of system values