Break off a chunk of local RAM to serve the M0 processor.
Adjust Makefile_inc.mk to serve both M0 and M4 targets through the LPC43XX_TARGET variable.
Consolidate hackrf_usb and hackrf_usb_rom_to_ram projects -- with generation of SPIFI binary by default.
Remove MAX2837_FREQ_NOMINAL_MHZ #define -- it must be updated now that IF is adjustable. So I pushed the calculation directly into the two places it was used.
Don't put MAX2837 into shutdown mode -- powering up takes a bit too long (500us for PLL to stabilize). Will need to revisit, because the MAX2837 chews up significant current (35 to 45mA) when not in shutdown.
Remove excess calls to max2837_start() and max2837_stop().
Reduce drive strength from clock generator (Si5351C) to first mixer (RFFC5072). This reduces every-50MHz spurs in RX by 10 to 15dB.
Additional CGU register decoding in dump_cgu.py.
Changes due to CGU header API changes.
Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
Do conversion from unsigned to two's-compliment inside FPGA.
Slow down edges of data lines coming from CPLD.
Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this.
Updated CPLD bitstream with two's complement I/O and sample ordering fix.
Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values.
Remove CPLD SVF file, as it's not used by anybody (as far as I know).
Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
Add M0 linker script.
Relocate SGPIO pin configuration -- it only needs to be done once.
Fix return value on SGPIO decimation function.
Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files.
Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now...