i2c: tegra: Fix i2c unknown interrupt issue

writes to modules on APB bus may complete out-of-order. need
to guarantee that the write is completed by reading it back.

read I2C_INT_STATUS back right after writing the current int status
in the isr to make sure the clear operation of I2C_INT_STATUS is
done before the interrupt is re-enabled.
the same also done for DVC_STATUS.

bug 980763

Change-Id: I34f18804d530ccadf561fe1736552b6a4dd6e4ce
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/101925
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Endeavoru V2 aka HOX Plus memory timings
mmc: wakeup panic fix aka sdio_irq_thread

check if host->sdio_irq_thread is NULL before wake_up_process() is
called on host->sdio_irq_thread
mmc: core: fix possbile memory leak
video: tegra: clock/power ungate when reading sd registers
video: tegra: use phys_addr_t to hold phys addr

Conflicts:
	drivers/video/tegra/nvmap/nvmap_dev.c
video: tegra: apply cmu changes only when active
video: tegra: fix explicit null dereference
video: tegra: fix refresh rate function
video: tegra: always set cmu table when enabling cmu
video: tegra: go idle before suspend
video: tegra: reset host clients on register
video: tegra: export nvhdcp state using ioctl

Conflicts:
	include/video/nvhdcp.h
nvmap: implement deferred cache maintenance

Defer maintenance till pin or unmap. Handle multiple deferred
operations in batches to flush faster. Enable full L1/L2 flush
if batch is big enough.

bug 983964
bug 994226

Reviewed-on: http://git-master/r/138931
(cherry picked from commit 01d0145ea95c7f98aa4bea3f71962872ba70bdfc)
Change-Id: I29bc82ded1fd7282426e8f161cc55e17f67fc649
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/171176
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
board-x3-power: lower smps1 and smps2 regulator max voltage
configs: update configs