ARM: sunxi-mmc: Remove dead code / vars

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Don't mix dma_alloc_writecombine with free_coherent

Use the less exotic (and correct on older ARM cpu cores) dma_alloc_coherent,
note this makes no different on ARMv7.

Also pass in our device pointer to the dma functions, instead of NULL.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Get regulator first

Getting the regulator may cause our probing to be deferred, so do it first,
otherwise we may end up calling things like clk_get multiple times until
we succeed, leaking references.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Properly set caps

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Turn on IDMA controller after all setup is done

Specifically set the interrupt mask, and the segment list address before
turning it on. Note the code for setting the segment list address is moved
to a different function entirely, as that needs to be done only once.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Add SD/MMC 0 host device for Allwinner A20

HdG:
Changed drive strength for the mmc / sdio pins from 0 to 3, this is necessary
to make high frequency sdcard/sdio modes work reliable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Enabe MMC 0 for CubieBoard2

HdG:
Dropped the unneeded "reg = <0>;" and related parts from the vcc_3v3_reg
section.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Enable MMC 0 on the cubietruck

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: dts: Correctly set sdc0 interrupt type, fixing all the hangs

This is a very small patch, but it took me 2 days to debug, still it was
worth it as this patch has big results, mmc cards now work reliable!

The problem is that the interrupt type for the sdc controller was set
to rising edge (all interrupts are setup this way in sun7i-a20.dtsi, which
likely is wrong).

Setting it to rising edge causes missed interrupts:

1) A request with data is send to the controller
2) The controller finishes the CMD phase of the transaction, this causes
   a bit to be set in the interrupt status register, but this bit is masked
   out, so no interrupt
2) The IDMA controller finishes transferring the data from the request,
   setting its tx or rx complete interrupt status bit, this does cause an
   interrupt
3) The ISR reads the interrupt status register
4) While the ISR is running the hardware completes the data phase of the
   transaction and/or the auto-stop and sets the SDXC_DataOver and/or
   SDXC_AutoCMDDone bits) since this is a request with data these bits
   cause an interrupt, note the interrupt line is already high at this point,
   so no edge!
5) The ISR writes back the interrupt status it has just read, clearing the
   IDMA controller tx or rx complete interrupt status bit. Note the interrupt
   line does not go low, as the SDXC_DataOver and/or SDXC_AutoCMDDone bits have
   not been cleared
6) The ISR exits and does not re-trigger since the interrupt type is set to
   rising edge
7) The block layer now hangs waiting for a request which never completes
   (timeouts are handled in hardware and sets another interrupt status bit)

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: dts: sunxi: Fix sunxi-ahci not working on sun4i

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Implement support for mmc on sun4i

While dealing with the amount of bits in the data buf size register anyways,
also properly use all 16 bits of the data buf size on sun5i / sun7i,
rather then only using 15 bits.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mci: Cleanup / rewrite interrupt handling + fix locking

-use the CmdDone interrupt to wait for CmdDone on RespTimeout instead of
 busy waiting
-remove wait and the WAIT_ enum, all different normale values are treated
 equally. Only the DMA flag effectively has any meaning, so replace the
 WAIT_ enum and var with a wait_dma flag
-we only ever check raw_int for SDXC_IntErrBit, which is always set in
 REG_IMASK when we've a request pending -> only check msk_int
-error is only set when int_sum contains SDXC_IntErrBit, and it is used
 inconsistenly, always check int_sum for SDXC_IntErrBit when checking for
 errors
-put locking around *all* shared data accesses done from the tasklet / irq /
 req submission paths, remove unnecessary smp_wmb-s
-change smp_wmb in sunxi_mmc_init_idma_des to a regular wmb, this is
 for io / regular mem data access sync, and we need this on non smp too
-do all irq / imask clearing from the irq handler where it belongs
 (drop it from sunxi_mmc_request_done)
-merge sunxi_mmc_request_done code into sunxi_mmc_finalize_request
-always use readl / writel to access all registers (they are all 32 bits)

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi-mmc: Add some fixes from the old allwinner sunxi-host driver

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun7i: dt: Fix interrupt trigger types

The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A20 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sun6i: dt: Fix interrupt trigger types

The Allwinner A31 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A31 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
net: allwinner: emac: Add missing free_irq

The sun4i-emac driver uses devm_request_irq at .ndo_open time, but relies on
the managed device mechanism to actually free it. This causes an issue whenever
someone wants to restart the interface, the interrupt still being held, and not
yet released.

Fall back to using the regular request_irq at .ndo_open time, and introduce a
free_irq during .ndo_stop.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
net: stmmac: Enable stmmac main clock when probing hardware

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
net: stmmac: Honor DT parameter to force DMA store and forward mode

"snps,force_sf_dma_mode" is documented in stmmac device tree bindings,
but is never handled by the driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
net: stmmac: Use platform data tied with compatible strings

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
net: stmmac: sunxi platfrom extensions for GMAC in Allwinner A20 SoC's

The Allwinner A20 has an ethernet controller that seems to be
an early version of Synopsys DesignWare MAC 10/100/1000 Universal,
which is supported by the stmmac driver.

Allwinner's GMAC requires setting additional registers in the SoC's
clock control unit.

The exact version of the DWMAC IP that Allwinner uses is unknown,
thus the exact feature set is unknown.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>