Adding arm and Ten GbE modifications to l8.

This bof file has an arm sequence update and adding an
'and' gate before tx_valid on the Ten GbE out.
The arm signal now is confirmed high for only one clock
and then given a 100 clock delay before entering triggering
the sync generator.
Adding changes to h16k_ver104.mdl

This is only changing the clock rate to meet lower
bandwidth specs.  No other changes have been made.
Merge branch 'master' of github.com:casper-astro/vegas_devel