cappuccino/lsu: simplify lsu_except_dbus_o
dcache: enable RAM bypass registers

This still required for the case where several < word writes
are written into the same word with no clock cycles between them.
cappuccino/lsu: remove tangling dc_cache_inhibit wire

The real wire is called dmmu_cache_inhibit
cappuccino/lsu: add store buffer

This pretty large patch adds a store buffer to cappuccinos lsu.
It's a very simple and naive one, where all stores are done into
a fifo. As long as the fifo is not full, execution are not
stalled until a load operation is performed.
There is no logic to check if the incoming load is in the
store buffer, the pipeline is unconditionally stalled
until the FIFO is empty.

This also moves all write related bus logic to the lsu,
i.e. the cache do not perform any bus operation related
to writes.

A bit of special handling is required to get the right offending
PC when a bus error happens for a store.
Since the pipeline isn't stalled, we need to save the right epcr
into the store buffer in order to match the PC to the store that
caused the bus error.
And also because the pipeline isn't stalled, instructions after the
offending store will have time to execute before the execution happens.
This is a change in behaviour from all other or1k implementations,
but not really against the arch spec.
A data bus error exception is anyways a "game over" situation,
so as long as you provide the user with the important information
of which address caused the error and at which PC did it happen,
it should be fine.