* Fixed register live range in for-loops:
  o Loop counter node is "left", not "right",
  o End-value register needs explicit sync.

Without these changes, allocating registers in hlcg.a_cmp_reg_loc_label (at the end of loop) could reuse counter or end-value register, resulting in invalid code.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@24924 3ad0048d-3df7-0310-abae-a5850022a9f2