wb_intercon: replace rdt/sdt with wb spec compliant name (dat)

Using non-standard names on signals in a standardised bus is
confusing for users, so that should be avoided.
However, the naming convention (sdt/rdt instead of dat for
slave data), served a purpose. It avoids the issue of two
signals having the same name when interconnectnig cores.

This patch takes a different approach and insert direction
markers into the signal names in modules where interconnect
occurs. The markers are: 'm2s' for 'master to slave' signals
and 's2m' for 'slave to master' signals.
Merge pull request #3 from skristiansson/for-openrisc

wb_intercon: replace rdt/sdt with wb spec compliant name (dat)
or1200-generic: Update interface in wb_intercon
cores: add simple 8-bit gpio core

Cleaned up version of the old orpsocv2 gpio core.
The "configurable" width have been removed, since the
layout of data and dir registers didn't make any sense.
If wider width is desired, it's expected to instantiate
several verisons of the core instead.
The tristate logic have been moved outside of the core,
and an output enable signal has been added instead.
The old core only checked for wb_stb_i and not wb_cyc_i,
that has been fixed.
cores/mor1kx: use 'version' instead of deprecated 'branch' option

When the the version option was introduced the branch option is
no longer recognised and will be ignored. Even though there is
a fallback to master when there is no version option stated,
explicitly stating it makes it more clear for users what to modify
to get a certain version.
cores: add diila - Device Independent Integrated Logic Analyzer core
cores: add wishbone to avalon bridge core

Core for bridging between wishbone and avalon busses.
Bursting is not yet supported.
wb_intercon: Add wb_intercon generator

wb_intercon_gen creates a verilog wrapper module that instantiates
wb_mux and wb_arbiter components to form an interconnect block.

As input, a configuration file is used for specifying masters, slaves
and their configurations.
sockit: add wishbone control to clkgen

This allows controlling the reset signals over the wishbone bus.
The intention is that programmable PLLs could be controlled over
this in the future as well.
sockit: re-enable jump to 0x100 in ROM
sockit: update README
Merge branch 'master' of github.com:openrisc/orpsoc-cores

Conflicts:
	systems/or1200-generic/bench/verilog/orpsoc_top.v
	systems/or1200-generic/bench/verilog/wb_intercon.v