First version of c-file printing. TODO: fill int node[??] automatically
Writing C-file, writing -names.txt, added TLUT in the VHDL names, NEXT:Output Xilinx c-file
Merge commit 'de018fe93d688bb6cbde8a616e505e79d98fdf60' into phase2
Clearer printout of results
Xilinx c-file now generates a bitwise C-program
Updating the make file so the c-file function is actually built and changed the c-file structure to better fit the tool flow (and Xilinx)
finalizing Xilinx c-file print-out
rewrite genparameters to use blif file; less dependent on our parsing of the verilog/vhdl format
tcam example fix
convert signal names to lowercase
updated documentation for genparameters rewrite
usage information for genParameters added
Merge branch 'gen_parameters_rewrite' with itself
clean work directory before running test
sort inputs of blif alphabetically
better support for xilinx integration, changed c-file and vhdl file header
add virtexIIpro flow to the git repository, improved xilinx c-file output
Improved output
working Virtex II Flow
clean up Virtex II Pro flow, bash map added to source, tmap.py and generateTMAPMake.py added to python scripts, removed lut_locations.h (included in locations.h)