missed a spot where busWidthWords was assumed to be 2
removed AxiSlaveTest from PcieToAxiBridge
a bit of cleanup of PcieToAxiBridge
Improved PCIe transport level packet trace

* Timestamp the packets with cycle count
* Filter out broadcast messages (which are sent on the desktop PCIe bus).
Fixed two PCIe protocol problems

* Use typeclass and nosnoop value from request in completions returned from PortalEngine
* Use busWidthWords when computing the number of dwords to read in AxiSlaveEngine
Use 16MB BAR2 on Virtex7 boards (already made the change for Kintex7 boards)
busWidth can be as high as 128 bits in AXI buses
PCIe was only interrupting host based on the first portal's interrupt lines

Fixed that problem, also changed to a Bool for the interrupt rather than a Bit#(0).
print out pcie rcb_mask, max_read_req_bytes, max_payload_bytes
print out inter-transaction latency in tlp.py
make program does not build the .bit file