.bit source deployment of ise workflow now checks existence of files before deployment, .bit generation is skipped if all files existed already, board compatibility now on basis of ise version code documentation of generated drivers
continued progress towards zed support, fixed issues with file deployment
zed build running through! (added different sdk visitors for each board, moved gpio block to generic)
fixed smaller issues in generation for zed board, the gpio example and protocol decoding
copying of files to board folder moved to board backends, new interrupt setup for zed board
removed interrupt port for leds, some improvements for parser and gpio handling (work in progress)
simplified bdl model, source imports now get normalized (allowing relative paths in .bdf files)
naming of components now more homogeneous, clarified package structure
adjusted backend architecture graphic, fixed a bug in the c-model unparser
removed backend from the bdl model (it is configured via cli parameter)
reworkes gpio modelling, added clock and memory models for improved mhs generation, improved parameterized usage help, some documentation (esp chapter 4.2)
cleaned up some warnings
fixed a bug with the clock generator
Updated documentation, updated commons.lang to 3.1, cleanup and some smaller bugfixes
rudimentry (and probably wrong) cdma architecture for zedboard driver
documentation, fixed an issue with memory allocation, calrified some debug messages
support for additional source files (.v, .ngc)
Tutorial documents and a new sample design AxiFIFO with generated core
Merge branch 'development'

Conflicts:
	changelog
	src/main/java/de/hopp/generator/Main.java