Read delay slots as instructions not mem.

Just in case - could be a jump target, maybe?  Never seen it, though.
Jit unaligned reads/writes.

This mostly just improves perf on debug, not really on the map for release.
Fix CompShiftVar for x86 jit.

In case rd == rs, need to load ECX first.  I can't find anything
else wrong with it for it to be disabled.
Merge pull request #568 from unknownbrackets/jit-minor

Jit: lwl/lwr/swl/swr, shift var