Perf: Restore correct CPU's PMU counters after power collpase

Since the L1CC PMU's are per CPU, the variable to detect if a CPU
came out of powercollapse also needs to be a per CPU variable. This
ensures that we reset and restore the correct CPU's PMU counters.

Change-Id: I02273df2eff9f6d88d68f46a7752c107b290a8ef
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Make L1 PMU IRQ name target independent

Remove target name from IRQ string, since the percpu IRQ API
is shared with all Qcomm targets.

Change-Id: Id0e7d9267654b373e9360806900259e00bf5a0ab
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Change IRQ functions for CPU variants

Unicore targets can't use the percpu IRQ API,
so fallback to the generic versions of the functions
at init.

Change-Id: Id3db611fe4a7e0dcfbeb2f3ae08a5f7189132034
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Add generic IRQ handlers for ARMv7 PMU's

For ARMV7 based PMU's implemented outside Qcomm, default
to the generic IRQ handlers to maintain original behavior.

Change-Id: Ic65379104cc708460f2f84c00ea86c1e284bbd29
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Let platforms decide IRQ request methods.

This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.

Instead of adding extra parsing to the ARM generic perf_event file,
this patch moves it to the 'mach' directory where targets types
can be detected in an implementation specific manner.

The default behavior is maintained for all other ARM targets.

Change-Id: I041937273dbbd0fa4c602cf89a2e0fee7f73342b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: Perf: Differentiate between L1 and L2 PMU IRQs

The L2 perf code shares some resource reservation functions
with the L1 perf code. In these functions, use defaults
only if they're not defined for the L1 and L2.

Change-Id: I5a390aa0085694466800db78b51837556aa12cdd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Assign proper routine to free IRQ

If the platform descriptor does not provide
its own free_irq function, default to the fallback
version.

Change-Id: I185186bf68b79e2dbfba77b0de66eb4daaf32fb8
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: perf: Relax Column exclusion checks for L2CC events

Identical L2CC events with the same register, code and group
can be set up with individual origin filters. The hardware
restricts counting only for identical register and group settings
but a different value for the event code.

Detect such identical events and let them pass the constraint
checks.

Change-Id: I609defb5c5b070b1007b2e7db9e2d8315d2ba1d7
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: perf: add debug patch logging framework

Provide a mechanism to track which msm perf patches
are present in a kernel. Some kernel branches do
not include all patches which causes problems trying
to debug perf issues. This framework provides a way
to keep track of which patches have been included
in a build.

Change-Id: Ib8ef311454564c4609d94decd93e039c80104275
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Restore counter after powercollapse for generic ARM PMU's

The MSM SoC's which have ARM's CPU's can power collapse. Ensure
the CPU side PMU's correctly restore the counters after coming
out of power collapse.

Change-Id: I544a1dd8ced26f726ba115d14867d9e34c2a7944
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Toggle PMU IRQ when CPU's are hotplugged

When a CPU is hotplugged out while a perf session
is active, disarm the IRQ when the CPU is preparing
to die. This ensures that perf doesn't lock up when
it tries to free the irq of a hotplugged CPU.
Similarly, when a CPU comes online during a perf session
enable the IRQ so that perf doesn't try to disable
an unarmed IRQ when it finishes.

Change-Id: Ic4e412e5f1effae0db34a3e4b5e7e5c65faed2a0
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Correct irq for CPU hotplug detection

The platform data was requesting the wrong number,
it should request the first perf irq item.

Change-Id: I4a25b4704ed9e76172c6b0d4ca4b28a3286ab2ad
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm_fb: display: add mutex to video_off

It is possible  that pipe_commit still be issued by
frame work after suspend had been started. Therefore
mutex lock within video_off is necessary to prevent
race condition from happening between these two threads.

Change-Id: I57f51744c1654d6def8664c492035631a5b7081e
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm: acpuclock-8064: Lower max L2 speed to 1134MHz

There are some testing showing that L2 at 1188MHz may cause
some stability issue. Lower the max speed to 1134Mhz until
the root cause is found.

Change-Id: I327c33c72ea0327e269d7839fadfb25ac715408b
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
msm: camera: Update debug data in vfe driver

there is a mismatch between actual VFE command and the
debug data.Update debug data in vfe driver to fix this
issue.

Change-Id: I3727cd8e5c7095d462b5532cd45f118ad7a6504c
CRs-Fixed: 452004
Signed-off-by: Suresh Vankadara <svankada@codeaurora.org>
ASoC: msm: Mixer control to update the sample rate of HDMI interface

Updating the sample rate for the compressed stream playback of the HDMI
interface through the mixer control.

Change-Id: Ib7b01f490f5e209512433a82faf96af0a3a810bd
Signed-off-by: Aviral Gupta <aviralg@codeaurora.org>
msm_fb: display: fix fence fd list be put twice

msm_fb_wait_for_fence() will put fence fd list if sync_fence_wait()
failed. After that same fd list wil be put one more time. This
cause a fd put twice and cause system crash at the time fd
was closed.

Change-Id: If6a358e051c98841e34c23d81098243003ef0836
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
wcnss: Add support for nv bin download at coldboot

NV bin is downloaded when wlan driver is loaded. This change
adds support for NV bin download during coldboot of WCNSS and
thus much before wlan driver is loaded. NV bin id not downloaded
by platform driver during SSR.

Change-Id: I070aae4270c54a3af4d4c0a24897e8c0c9cbfaa5
Acked-by: Rajesh Chauhan <rajeshc@qca.qualcomm.com>
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
media: dvb: Fix secure demux application load check

To deduce whether secure demux is available, an attempt is made to
load the secure demux appliction during module initialization.
The loading process retrieves the application from filesystem.
When kernel configuration is set so that the module is built-in
as part of the kernel image, filesystem is not yet available
and loading fails.
This change moves the loading attempt from initialization
to first usage of status query, which occurs after device
is opened by user-space and filesystem is sure to be available.

Change-Id: I22d24054196f6068bf28e2ba6f2a4da6a9340730
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
msm_fb: Update MDP fence wait behaviour

The current fence wait times out too early in cases where the GPU
is under a heavy workload. Change this behaviour to warn and wait
for a longer time for GPU to complete it's work.

Change-Id: I8b20c22733a77c1aaea4a1fd1e4daaa14b5ec2fd
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>