daily update
daily update
	* symtab.h (Symbol::clear_version): New function.
	* symtab.cc (Symbol_table::set_dynsym_indexes): Don't set object
	is_needed by weak references.  Clear version for symbols defined
	in as-needed objects that are not needed.
	* ld-elfvers/vers.exp: Add -Wl,--no-as-needed to all tests
	linking against shared libraries.
	* ld-elfweak/elfweak.exp: Likewise.  Enable for x86_64-linux.
	Build main1.o using $picflag.
bfd/
	* elflink.c (_bfd_elf_make_dynamic_reloc_section): Override
	sh_type according to is_rela.
ld/testsuite/
	* ld-elf/rel.c, ld-elf/relmain.c, ld-elf/relmain.out: New test.
	* ld-elf/shared.exp: Build and run it.

ld/testsuite/ChangeLog:

2013-03-20  Will Newton  <will.newton@linaro.org>

        * ld-elfvers/vers.exp (objdump_symstuff): Sort objdump output
	based on the symbol name rather than address.
	* ld-elfvers/vers1.sym: Reorder contents to match changes to vers.exp.
	* ld-elfvers/vers15.sym: Likewise.
	* ld-elfvers/vers18.sym: Likewise.
	* ld-elfvers/vers21.sym: Likewise.
	* ld-elfvers/vers9.sym: Likewise.
Enable --gc-sections test cases for aarch64*-*-*
* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.

* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb)  field coding types
and use it to encode register pair numbers when required.

* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.

* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.

* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
	PR gas/15082
	* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
	from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
	tic6x_operand_xregpair operand coding type.
	Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
	opcode field, usu ORXREGD1324 for the src2 operand and remove the
	TIC6X_FLAG_NO_CROSS.

	* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
	cross-path.
	* gas/tic6x/insns-bad-1.l: Update expected output.
	* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
	cross-path.
	* gas/tic6x/insns-c674x.d: Update expected output.
daily update
	* dwp.cc (Dwp_output_file::add_contribution): Avoid signed/unsigned
	comparison warning.
	* layout.cc (Layout::create_dynamic_symtab): Avoid "may be used
	uninitialized" warning.
	* layout.cc (Layout::set_segment_offsets): Accept writable .text
	segment when omagic.
	PR sim/15286
	* elf32-arm.c (bfd_arm_get_mach_from_attributes): Identify XScale,
	iWMMXt and iWMMXt2 processors from attributes.
	* pe-dll.c (process_def_file_and_drectve): Don't handle VC
	generated C++-symbols as stdcall/fastcall.
	* coffgen.c (coff_real_object_p): Make global.
	* peicode.h (coff_real_object_p): Add prototype.
	(FILHDR): Defined for COFF_IMAGE_WITH_PE as
	external_PEI_IMAGE_hdr structure.
	(coff_swap_filehdr_in): Handle variable header-size.
	* peXXigen.c (_bfd_XXi_swap_aouthdr_in): Just handle amount
	of directory-entiries as specified in pe-header.
	PR gas/15282
	* tc-avr.c (mcu_has_3_byte_pc): New function.
	(tc_cfi_frame_initial_instructions): Call it to find return
	address size.
	* elf32-h8300 (h8_relax_section): Add new relaxation of mov
	@(disp:32,ERx) to mov @(disp:16,ERx).
	(R_H8_DISP32A16): New reloc.
	Comments added and corrected.
	* reloc.c (BFD_RELOC_H8_DISP32A16): New reloc.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

	* ld.texinfo (H8/300): Add description of relaxation of
	mov @(disp:32,ERx) to mov @(disp:16,ERx).

	* ld-h8300/h8300.exp: Add new relax-7 test on ELF.
	* ld-h8300/relax-2.s: Add other direction and .w/.l variants of
	mov insns.
	* ld-h8300/relax-2.d: Update expected disassembly.
	* ld-h8300/relax-7a.s: New: tests for mov @(disp:32,ERx) -> mov
	@(disp:16,ERx).
	* ld-h8300/relax-7b.s: New: Likewise.
	* ld-h8300/relax-7.d: New: expected disassembly.

	* config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov
	@(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc
	R_H8_DISP32A16.
	* config/tc-h8300.h: Remove duplicated defines.
gas/ChangeLog:

2013-03-21  Will Newton  <will.newton@linaro.org>

	* config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
	pc-relative str instructions in Thumb mode.

gas/testsuite/ChangeLog:

2013-03-21  Will Newton  <will.newton@linaro.org>

	* gas/arm/thumb2_relax.d: Strip out invalid pc-relative strs.
	* gas/arm/thumb2_relax.s: Likewise.
	* gas/arm/thumb32.d: Likewise.
	* gas/arm/thumb32.l: Likewise.
	* gas/arm/thumb32.s: Likewise.
	* gas/arm/thumb2_str-bad.d: New file.
	* gas/arm/thumb2_str-bad.l: Likewise.
	* gas/arm/thumb2_str-bad.s: Likewise.
daily update
	* ld-elf/init0.s: Add alloc attribute to .section directive.
	* ld-elf/fini1.s: Likewise.
	* ld-elf/fini2.s: Likewise.
	* ld-elf/fini3.s: Likewise.
	* ld-elf/finin.s: Likewise.
	* ld-elf/init0.s: Likewise.
	* ld-elf/init1.s: Likewise.
	* ld-elf/init2.s: Likewise.
	* ld-elf/init3.s: Likewise.
	* ld-elf/initn.s: Likewise.