V4 regalloc: fix cycle scheduling in resolve phase.

When resolving differences in register/spill-slot assignment between
basic-blocks, dependency cycles can occur. Those cycles have to be
scheduled after non-cyclic dependencies.

This also removes a assertion that only held when the cycle was 2 long,
but would incorrectly fire for longer cycles.

Change-Id: I519fd43bbf117d3480e4169ff363e97a9ec450f8
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
V4 regalloc: correct life-time hole handling.

When a life-range is active, but does not cover a position, it means
that it is inactive. When going from active to inactive (or vice-versa),
a (un-)spill is only needed when there is a stack-slot allocated to the
range. It is valid to not have a stack slot: when no call is done, or
when the register pressure does not push the end of the hole onto the
stack.

Change-Id: I5f5a05181c8cb384f031538dbefd7d11de682b8d
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
V4 JIT: change the stack layout.

The saved register area (used to store values in registers that need to
be passed by reference in a function call) is now right behind the
callee saved register area. This means that the stack now has two
"parts": a JavaScript part with the function call arguments and the
locals, and a "C++" part that holds saved registers which do not need to
be garbage collected.

This also fixes a bug where the size of the CallData was not taken into
account when calculating the offset for the saved registers.

Change-Id: If0af072f3299176c54ad33710e7d15bc9d26ae8b
Reviewed-by: Lars Knoll <lars.knoll@digia.com>