mailbox: add documentation to core code and headers

The current mailbox code lacks any meaningful documentation,
making life hard for any new users to understand the API/usage.
Hopefully, this patch adds enough basic info for the developers.

This patch does not touch any code pieces, it is strictly limited
to documentation and code comments.

Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: DRA7: clock: Fix the wrong ABE PLL lock frequency

The ABE PLL (used by ATL) was wrongly locked at twice the frequency.
Fix it and also set the dpll_abe_m2x2_ck rate explicitely so that we
have m2 set to 1.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
ARM: OMAP4+: Init the target pwrdm state before the pwrdms are setup

Fix the wrong init of pwrdm target state which is done *after*
the pwrdms are setup. Do it instead *before* the pwrdm setup so
it has an affect.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
iommu/omap: Remove unnecessary null pointer check

The pointer obj is dereferenced in line 146 and 149 respectively, so it is not
necessary to check null again in line 149 and 175. And I have checked that all
the callers of these two functions guarantee the parameter obj passed is not
null.

Signed-off-by: Cong Ding <dinggnu@gmail.com>
Acked-by: Ohad Ben-Cohen <ohad@wizery.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
iommu/omap: fix checkpatch warnings in omap iommu code

This patch fixes the checkpatch warnings in omap iommu
code, most of them are related to broken strings.

Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox: remove unused function prototype

The internal function mailbox_init_seq is not defined
anywhere, so clean up its prototype declaration.

Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox: remove mailbox_type_t from mailbox_ops

The mailbox_type_t is a legacy carry-over from the OMAP mailbox
code. It was primarily used to distinquish the hardware FIFO type
between OMAP1 & OMAP2+ SoCs. The type field serves no purpose in
the common mailbox ops, and has therefore been cleaned up.

The OMAP & DBX500 mailbox client drivers do have an internal type
field in their respective private mbox structures, and is used for
differentiating the mailbox types or register sets.

Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox: introduce irq_flags per mailbox

Leave it to the individual driver implementation to decide the
irq_flags needed when requesting the irq.

Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: OMAP2+: add user and fifo info to mailbox platform data

The different generations of OMAP2+ SoCs have almost the same
mailbox IP, but the IP has configurable parameters for number
of users (interrupts it can generate out towards processors)
and number of fifos (the base unidirectional h/w communication
channel). This data cannot be read from any registers, and so
has been added to the platform data.

This data together with the interrupt-type configuration can be
used in properly figuring out the number of registers to save
and restore in the OMAP mailbox driver code.

Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox: add support for multiple instances

The current mailbox driver core is designed to have only one mailbox
h/w block in the system, but this is very unrealistic. Support has
been added for multiple instances of same or different mailbox h/w
blocks by adding a containing mailbox_device structure. The mailboxes
contained within a h/w block are associated with this mailbox device
structure. The mailbox drivers have to create this mailbox device object
and register their mailboxes with this device.

The design includes changing the mailbox_register/unregister functions
to allow the registration and deregistration of mailboxes using a
containing mailbox device object. Function ops are added per mailbox
device as well, to have flexibility in each individual mailbox device
implementations. The mailbox startup code is reconfigured to use both
the mailbox_device and mbox startup/shutdown ops accordingly.

While at it, modify the OMAP & DBX500 mailbox drivers to adapt to
these new API changes.

Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox/omap: add support for parsing dt devices

Logic has been added to the OMAP2+ mailbox code to
parse the mailbox dt nodes and construct the different
mailboxes associated with the instance. The design is
based on gathering the same information that was being
passed previously through the platform data, except for
the interrupt type configuration information.

Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: dts: OMAP2+: add mailbox nodes

The mailbox DT node data has been added for OMAP2420,
OMAP2430, OMAP3430/OMAP3630, OMAP44xx, OMAP54xx and
AM33xx devices.

The mailbox static device initialization logic is also
adjusted for a DT boot.

Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox/omap: check for status of platform_get_irq

The IRQs have to be defined in both the hwmod file as well
as the DT node (depending on a non-DT or DT boot). The
status of the platform_get_irq function therefore needs to
be checked to make sure the irqs are defined for the mailbox
platform device for the probe to be successful.

Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'platform-base-3.8.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into mailbox-linux-3.8.y

Merge platform base tree for adding DRA7xx mailbox support. The boot
on DRA7xx with this branch requires a ramdisk, a MMC-based filesystem
support is only available in branch ti-linux-3.8.y of integration
tree, git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git

* 'platform-base-3.8.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (89 commits)
  ARM: OMAP4+: Init the target pwrdm state before the pwrdms are setup
  ARM: DRA7: clock: Fix the wrong ABE PLL lock frequency
  ARM: DRA7: dts: Remove the non existent l3_main_3 entry
  ARM: DRA7: dpll: No freqsel on DRA7
  ARM: DRA7: dpll: Lock GMAC PLL at boot
  ARM: DRA7: dpll: Lock ABE PLL according to ATL needs
  ARM: DRA7: id: Change control_id_code register address
  ARM: DRA7: Prevent any low power entry in suspend
  ARM: DRA7: Add the build support
  ARM: DRA7: Add PRM dev_inst module offset in global_warm_reset function
  ARM: DRA7: Enable framework initializations
  ARM: DRA7: hwmod data: Create initial DRA7XX SOC hwmod data
  ARM: DRA7: clock data: Add DRA7XX full clock tree and headers
  ARM: DRA7: powerdomain data: Add DRA7XX data and update the header
  ARM: DRA7: clockdomain data: Add DRA7XX data and update the header
  ARM: DRA7: PRCM: Add DRA7XX local MPU PRCM regsiters
  ARM: DRA7: CM: Add DRA7XX register and bitfield files
  ARM: DRA7: PRM: Add DRA7XX register and bitfield files
  ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
  ARM: DRA7: PM: Avoid all SAR save on dra7
  ...

Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: dts: DRA7: Add mailbox nodes

DRA7xx has 13 system mailboxes, add the DT nodes for
all these 13 mailboxes. The unused mailboxes have been
disabled, and only mailboxes 1, 5 and 6 are enabled.
The remaining mailboxes can be enabled when a usecase
arises and their irq/xbar numbers are identified.

Currently, the FIFO assignment and target processor
assignment data is added only for mailboxes 1, 5 and 6.
The data is chosen to match the current mailbox assignments
in IPC 3.x with MPU receiving interrupts using user id
2 on mailboxes 5 & 6, and user id 0 on mailbox 0.

NOTE: The DT node data uses specific interrupt numbers
for mailboxes 5 & 6 and the actual interrupts are raised
only when the corresponding crossbar registers are
programmed correctly.

Signed-off-by: G Anthony <a0783926@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
iommu/omap: add cache flushing operation for L2 cache

Signed-off-by: Ramesh Gupta <grgupta@ti.com>
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
iommu/omap: dmm fixes

This fixes the following:
  1. pgd and pte entries weren't getting flushed out leading to MMU faults.
  2. Cache invalidate was setting wrong size parameter to
     memory_regain_ownership leading cache invalidate function to fail.

Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
iommu/omap: disable mmu interrupts after the first fault

Signed-off-by: Guzman Lugo, Fernando <fernando.lugo@ti.com>
ARM: OMAP4: hwmod data: correct dsp mmu address range

The external address space for DSP starts at 0x20000000 in
OMAP4, all the addresses below this are internal DSP addresses.
Adjust for the same in the DSP device attribute data, which will
be supplied to the driver as platform data.

Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'platform-base-3.8.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into iommu-linux-3.8.y

Merge platform base tree for adding iommu support to OMAP5 and
DRA7xx SoCs.

* 'platform-base-3.8.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (245 commits)
  ARM: OMAP4+: Init the target pwrdm state before the pwrdms are setup
  ARM: DRA7: clock: Fix the wrong ABE PLL lock frequency
  ARM: DRA7: dts: Remove the non existent l3_main_3 entry
  ARM: DRA7: dpll: No freqsel on DRA7
  ARM: DRA7: dpll: Lock GMAC PLL at boot
  ARM: DRA7: dpll: Lock ABE PLL according to ATL needs
  ARM: DRA7: id: Change control_id_code register address
  ARM: DRA7: Prevent any low power entry in suspend
  ARM: DRA7: Add the build support
  ARM: DRA7: Add PRM dev_inst module offset in global_warm_reset function
  ARM: DRA7: Enable framework initializations
  ARM: DRA7: hwmod data: Create initial DRA7XX SOC hwmod data
  ARM: DRA7: clock data: Add DRA7XX full clock tree and headers
  ARM: DRA7: powerdomain data: Add DRA7XX data and update the header
  ARM: DRA7: clockdomain data: Add DRA7XX data and update the header
  ARM: DRA7: PRCM: Add DRA7XX local MPU PRCM regsiters
  ARM: DRA7: CM: Add DRA7XX register and bitfield files
  ARM: DRA7: PRM: Add DRA7XX register and bitfield files
  ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
  ARM: DRA7: PM: Avoid all SAR save on dra7
  ...

Signed-off-by: Suman Anna <s-anna@ti.com>

Conflicts:
	arch/arm/mach-omap2/common.h