soc/sdram: rename sdram signals for data bus prefix.
debugger: fix argument validation for memory writes.
debug: only hold mem_access high for one cycle.

It's only a single cycle needed to start the access that ends once ack
is raised.
rtl/fetch: fix fetch for multicycle accesses + debug.

When debugging we might start a fetch but with a single step we wouldn't
correctly advance the PC.
soc/sdram: wire up the SDRAM to the instruction bus.
decodeinstr: handle 16 GPR's correctly.