i965: Fix Haswell/CRW PCI IDs.

The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1).  This also meant no support for GT1 at all.

NOTE: This is a candidate for stable branches.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
intel: Fix an instance of mixed tabs and spaces

Fix a line to use only spaces. All adjacent lines were using spaces.  This
fixes weird indentation.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Add field intel_mipmap_slice::has_hiz

Performing a hiz operation with an ill-aligned rectangle primitive causes
GPU hanges on some hardware.  Later patches will disable hiz on individual
slices to avoid such hangs.

However, this patch introduces no behavioral change.  If `mt->hiz_mt` is
set, then this sets `has_hiz` for all slices in the miptree.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Add accessor functions for intel_miptree_slice::has_hiz

Add two new functions:
  intel_miptree_slice_has_hiz
  intel_renderbuffer_has_hiz

These functions are not yet used.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
i965: Add level,layer members to brw_blorp_mip_info

These will later be used to determine if hiz is enabled for the given
slice via intel_miptree_slice_has_hiz().

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
i965: Change signature of brw_get_depthstencil_tile_masks

Add two new parameters, 'level' and 'layer'. A later patch will pass the
new parameters to intel_miptree_slice_has_hiz().

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
i965: Fix typo in doxygen hyperlink

s/brw_state_upload/brw_upload_state/

Found because the link was broken.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Replace checks for hiz_mt with has_hiz accessors

That is, replace checks like `hiz_mt != NULL` with
`intel_miptree_slice_has_hiz(...)` where appropriate. This is necessary
because a later patch will selectively disable hiz on individual miptree
slices, and therefore `hiz_mt != NULL` will no longer be a valid
indicator.

This produces no behaviorial change because, currently, if a hiz miptree
is present then hiz is enabled for all slices in the tree.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Refactor selection of miptree tiling

This patch (1) extracts from intel_miptree_create() the spaghetti logic
that selects the tiling format, (2) rewrites that spaghetti into a lucid
form, and (3) moves it to a new function, intel_miptree_choose_tiling().
No behavioral change.

As a bonus, it is now evident that the force_y_tiling parameter to
intel_miptree_create() does not really force Y tiling.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Refactor selection of miptree's internal formats

Extract from intel_miptree_create() the logic for selecting
intel_mipmap_tree::format and ::etc_format into a new function,
intel_miptree_select_formats(). No behavioral change.

Now, intel_miptree_create() is short enough to be understandable.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
i965: Push stencil alignment w/a down to brw_miptree_layout()

Miptree creation has a workaround for separate stencil buffers.  After the
layout is created, we override the tiling to I915_NONE and align it 64x64,
the size of a W-tile.

Before this patch, the workaround occurs in an odd place:
intel_miptree_create(). After brw_miptree_layout() creates the layout,
intel_miptree_create() overrides the tiling and alignment as needed.

Rather than override something after it has been set, it's safer to just
set it correctly in the first place. To do that, this patch pushes down
the workaround into brw_miptree_layout().

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
intel: Document intel_mipmap_tree::total_width,total_height

I had to use a debugger to deduce what total_width/height really were.
This patch is for the benefit of those who come after so they don't have
to dig as hard.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
i965: Add padding to depth and hiz miptrees

There exist alignment restrictions for the rectangle primitive emitted
during hiz operations. This patch pads the miptree to prevent a correctly
aligned rectangle from writing to out-of-bounds memory.

We do not currently emit a correctly aligned rectangle, though. That
arrives in a later patch.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
WIP/intel: Disable hiz on individual miptree slices

TODO: Refactor common stuff
TODO: doc

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
WIP: HiZ ambiguate immediately after creation

See workaround docs.
WIP/i965/blorp: Align vertices for hiz ops
WIP/intel: Don't calculate hiz_offset separately from depth_offset

TODO: Explain why.
TODO: See the TODO's in the patch.
intel: Enable hiz on Haswell

This patch sets the flag. That's all.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>