block: Add Simple I/O scheduler
Adjust color calibration

Adapted from PA's default color calibration.

Signed-off-by: Derek Cannata <thederekjay@gmail.com>
Input: Send events one packet at a time

On heavy event loads, such as a multitouch driver, the irqsoff latency
can be as high as 250 us.  By accumulating a frame worth of data
before passing it on, the latency can be dramatically reduced.  As a
side effect, the special EV_SYN handling can be removed, since the
frame is now atomic.

This patch adds the events() handler callback and uses it if it
exists. The latency is improved by 50 us even without the callback.

Change-Id: Iebd9b1868ae6300a922a45b6d104e7c2b38e4cf5
Cc: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Benjamin Tissoires <benjamin.tissoires@enac.fr>
Tested-by: Ping Cheng <pingc@wacom.com>
Tested-by: Sedat Dilek <sedat.dilek@gmail.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Henrik Rydberg <rydberg@euromail.se>

Input: Improve the events-per-packet estimate

The events-per-packet estimate has so far been used by MT devices
only. This patch adjusts the packet buffer size to also accomodate the
KEY and MSC events.  Keyboards normally send one or two keys at a
time. MT devices normally send a number of button keys along with the
MT information.  The buffer size chosen here covers those cases, and
matches the default buffer size in evdev. Since the input estimate is
now preferred, remove the special input-mt estimate.

Reviewed-and-tested-by: Ping Cheng <pingc@wacom.com>
Tested-by: Benjamin Tissoires <benjamin.tissoires@enac.fr>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Henrik Rydberg <rydberg@euromail.se>
touchscreen: tweak some initialization parameters for better UI response

Signed-off-by: faux123 <reioux@gmail.com>
Signed-off-by: Derek Cannata <thederekjay@gmail.com>
overclocking: MSM S4-pro overclocking to 1.836 GHz

Signed-off-by: faux123 <reioux@gmail.com>
Signed-off-by: Derek Cannata <thederekjay@gmail.com>
Voltage Control: Voltage control for MSM S4-Pro SOC

Signed-off-by: faux123 <reioux@gmail.com>
Signed-off-by: Derek Cannata <thederekjay@gmail.com>
GPU Overclock: 8064 GPU Overclock to 487 MHz

Signed-off-by: faux123 <reioux@gmail.com>
Signed-off-by: Derek Cannata <thederekjay@gmail.com>
msm: acpuclock-krait: NULL terminate L2 table for find_cur_l2_level()

find_cur_l2_level() assumes that the L2 table is NULL terminated
when it has never been terminated. Therefore, if the rate that is
read from the hardware during boot is not found in the table we
will run off the end of the table and read potential junk values.
NULL terminate all the L2 tables so that the loop in
find_cur_l2_level() is guaranteed to terminate.

Change-Id: Ia5d0213000b44def35e388fd3cadf0293344257b
Reported-by: Laura Abbot <lauraa@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: acpuclock-krait: Fix PTE efuse address for acpuclock-8974

Correct the efuse address base and offset for 8974. Since the offset
is now different on 8974 than on other Krait-based targets, it's no
longer possible to hard-code it in acpuclock-krait.c. Instead, move
it into the QFPROM address passed from SoC specific files.

Since the PTE EFUSE is not yet used on 8974 to select different
frequency/voltage tables, this change should have no current
functional effect.

Change-Id: I26de7c9ce84e2873b883123f9fe420b3cb14e364
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: acpuclock-krait: Keep the secondary MUX input fixed

With use of the QSB clock source recently eliminated, only one
input of the secondary clock MUX is used on any target. Since
there is overhead involved reprogramming this MUX when changing
the CPU and L2 frequencies, change the code to just program the
MUX at boot.  Most noticeably, this removes a 1us delay from
every CPU and L2 frequency switch.

modified for Mako by faux123
Change-Id: I5cd8c981f1be49be7dbba1310d84df439e8be83b
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
acpuclock-krait: sync with CAF baseline for ease of patching later

Signed-off-by: faux123 <reioux@gmail.com>
Signed-off-by: Derek Cannata <thederekjay@gmail.com>
msm: acpuclock-8064: Add support for multiple speed and PVS bins.

Add support for 1.7 GHz and 2.0 GHz parts and their corresponding
L2 and memory bandwidth votes.

Support selecting different PVS tables based upon EFUSE speed bin
across all krait targets.

Change-Id: Ibbf6b5182fce0a9e92014883d07a35dee5f0d2a1
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
modified from CAF reference for Mako

Signed-off-by: faux123 <reioux@gmail.com>
Signed-off-by: Derek Cannata <thederekjay@gmail.com>
msm: acpuclock-8064: Lower VDD_DIG voltage vote for L2 at 384MHz

New characterization data shows that vdd_dig voltage for L2@384MHz
can be lowered to 0.95v. Update the data in this patch.

Change-Id: Ibdb8568eca4d4ed602c5a5fee2f433a098dfbdcd
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
msm-3.4: acpuclock: Add 8064v2 PVS voltage table data

Add PVS tables for 8064v2 speed bin 2 (2GHz).

Change-Id: Iceffba9d0718f263de6e0fb32a89ca7878ad8310
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: acpuclock-8064: Final PVS Table Data for 8064v2

Update data from preliminary values to final data.

Change-Id: I69f32ef1bc1a82f8a93c1d465e55116e2a718013
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: acpuclock-8064: Add support for 8064v1.1 FASTER PVS bin

Add updated PVS data.

Change-Id: I011241d3ea3943673a888cd0aeca925440500ff2
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: acpuclock-8064: Add PVS tables for 1.7 GHz parts

Add all seven PVS bins.

Change-Id: I6408e4f94b92ca70547817ba7a3c390b9f980ca7
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: boards: Enable Krait Retention.

Add SPM sequences to do Krait retention for 8960,8930
and 8064. Also added a new rpmrs level containing the
latencies and power measurements for this new low power
state.

CRs-Fixed: 369864
Change-Id: Ib30a9a978cf38b35037810a4001c9277837acd4c
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
acpuclock-8064: add OC frequencies for 'faster' binned CPUs

Signed-off-by: faux123 <reioux@gmail.com>
Signed-off-by: Derek Cannata <thederekjay@gmail.com>