xen: arm: remove dummy HYPERVISOR_arch_0 hypercall

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: panic if we cannot build dom0's p2m.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Don't take the domain lock for p2m operations.

P2M ops are covered by their own locks, and these uses of the domain
lock are relics of shadow-v1 code.

Signed-off-by: Tim Deegan <tim@xen.org>
Reviewed-by: Andres Lagar-Cavilla <andres@lagarcavilla.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Keir Fraser <keir@xen.org>
xen/arm: Initialize PERCPU variables at the beginning of start_xen

PERCPU variables rely on HTPIDR (TPIDR_EL2) which is in an unknown state when
a processor boot.

For the boot CPU, the first use of PERCPU is in setup_pagetables. So
initialize PERCPU and set the processor ID before.

Bamvor Jian Zhang observed this failure on the sun6i processor which does not
initialise HTPIDR and contributed a very similar patch.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
[ ijc -- added last para of commit message ]
xen/arm: Don't emulate the MMIO access if the instruction syndrome is invalid

When the instruction syndrome is not valid, the transfer register is unknown.
If this register is used in the emulation code (it's the case for the VGIC),
Xen can retrieve wrong data.

For safety, consider invalid instruction syndrome as wrong memory access.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
xen/arm: Allow secondary cpus to start in THUMB

Unlike bx, eret will not update the instruction set (THUMB,ARM) according to
the return address. This will result to an unpredicable behaviour for the
processor if the address doesn't match the right instruction set.

When the kernel is compiled with THUMB2, THUMB bit needs to be set in CPSR
for the secondary cpus.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
xen/arm: Clean up identify processor call for secondary cpus

The smp_processor_id() is set at the beginning of start_secondary. We don't
need to compute ourself the offset of the cpu data.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
xen: arm: remove unnecessary cache flush in write_pte

On a ARMv7/v8 SMP system the MMU is coherent

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
[ ijc -- dropped the associated dsb too ]
xen: arm: tweak arm64 stack frame layout

Correct definition of UREGS_kernel_sizeof and use it.

Correct adjustment of stack on entry and exit.

Add 64-bit versions of the build time checks for stack pointer alignment
correctness when pushing the stack frames.

Lastly, correct the padding in the stack frames to properly align the inner and
outer frames and also avoid an unnecessary 64bit padding field.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: rename 32-bit specific zImage field offset constants

This will help avoid confusion when 64-bit Image support is added.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: support for loading 64-bit zImage dom0

This is defined in linux/Documentation/arm64/booting.txt.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: support building a 64-bit dom0 domain

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: precalculate VTTBR_EL2 for a domain when setting up its p2m

Mostly just to help with upcoming vcpu_show_registers changes.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: improve register dump output for 64-bit guest (and more generally too)

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
xen: arm: support dumping 64-bit guest stack

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: show less words in a line of a stack trace in 64-bit builds

Words are twice as wide so this ensures that a line is still <80 characters.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: Set EL1 register width in HCR_EL2 during context switch.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
xen: arm: some cleanups to hypervisor entry code.

Tweak the case of some system registers for consistency.

There is no need to export return_to_hypervisor or return_to_guest.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
xen: arm: refactor 64-bit return from trap path

Refactor exit path to use a single "exit" macro similar to the entry path.

We can also remove the logic at "return_to_new_vcpu" which detects returns to
hypervisor mode -- seemingly trying to handle hypervisor threads which aren't
an thing which we have. The idle VCPUs do not take this path. This simplifies
the return_to_new_vcpu code, we also split it into 32- and 64-bit VCPU paths.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
xen: arm: handle traps from 64-bit guests

While there observe that we weren't ever restoring the outer stack frame, even
for 32-bit guests when running a 64-bit hypervisor! The outer stack frame
"only" contains most of the SPSR registers for 32-bit...

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>