DCache: Non-disrupting invalidation

On the edge of an invalidation request the cache started one
invalidation of the respective tag. By permanently acknowledging the
SPR requests, this had to happen immediately which might corrupt other
processing. Furthermore the edge triggering is not correct as two
succeeding invalidations happen without a low cycle of the spr bus
strobe signal.

The new implementation simply always acknowledges SPR requests while
the invalidation can take place, which is during idle and
invalidation. In all other cases the operation is delayed until the
state machine returns to IDLE. When an invalidation lasts longer, the
respective tag is repeatedly cleared, which is no problem.

Finally, the state machine has been reordered without breaking the
functionality, but for a clear code layout (not overwriting sequential
assignments) and readability.