fixed an error in understanding wire tmp = sig; where the assignment is really a continueous assignment defined in the Verilog Spec
add default path into data path for report_partition, and now it is the time to link FSM to data ports
need to store the extracted FSMs in separated module structures
store fsms in separated modules
consider fsms in partition
report_partition is working but need further investigation
Merge branch 'fsm' into dev