ASoC: wcd9304: avoid decrementing active channel count if already zero

During error cases, there might be situation, when slimbus channels
are being closed even when the number of active channels for
that DAI is 0. Avoid decrementing ch_act field if it is already 0.

Change-Id: Ie988eb049a20fc7cf5725ddc183ee1ae5fcb758d
Signed-off-by: Banajit Goswami <bgoswa@codeaurora.org>
msm_fb: display: Evenly balancing load on MDP ports

Moving RGB1 and RGB2 to AXI port 1. This fixes underrun issues seen
on External display while connecting and disconnecting HDMI. This patch
evenly balancing pipe loads on each port.

Change-Id: I2dc1166d04bb938f9e233a6de52f1a8a3fdd29e2
CRs-Fixed: 435458
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
ASoC: wcd9xxx: Fix the ANC CnP

Add virtual ANC widgets which are used to enable ANC
before PA is turned on, and to disable ANC before TX is
turned off.

CRs-fixed: 387904
Change-Id: I8c2fa670062f1486499c79653a2c223f7daba84f
Signed-off-by: Damir Didjusto <damird@codeaurora.org>
mmc: msm_sdcc: Fix SDCC-BAM, DML reset sequence

Resetting SDCC-BAM after reset of SDCC-DML causes
interface disconnect between SDCC-BAM and SDCC-DML
and lead to hang when SDCC driver initiates data
transfer in BAM mode. Modify the SDCC reset sequence
to reset SDCC-DML after reset of SDCC-BAM.

CRs-Fixed: 423399
Change-Id: Ia31d40e30cbf95befba3b1133a525a81903789f2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
(cherry picked from commit b745eeb229a476d81ee4177adfe168d3a35bda47)
msm: pm-8x60: save and restore CP15 registers

To prevent the Krait core configuration from being indvertently changed
when doing L2 power collapse, save a few CP15 registers and restore them
back after coming out of power collapse. This needs to be done after
switching the Krait from active freq to QSB clock source.

Before doing power collapse, the core0 clock switches over to QSB. However,
QSB can run at any frequency and the voltage required for that
frequency, needs to be ensured when coming out power collapse. If the
QSB clock at resume, is a higher frequency at than the QSB clock was at
collapse, then we may run the risk of running at higher clock with a
lower voltage.

Hence, switch to 1.0 V (safe vdd) when going into PC (after switching to
QSB clock source) and the SPM would resume at 1.0V. After the core
starts running, restore the CP15 registers and switch to the previously
saved active voltage, before switching clocks to the active frequency.

This is applicable only for APQ8064.

Change-Id: I75a70f5e07bd581fc8028bed79de7ee796f4c411
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: pm-8x60: Fix bug where device enter low power mode

An incorrect ordering in the check of allowed modes, results in
standalone power collapse not getting selected when the secondary
cores are online.

Change-Id: Idc7177b78bd0ce7563cc27afbf6c12d3bc1f9f9a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: boards: Enable Krait Retention.

Add SPM sequences to do Krait retention for 8960,8930
and 8064. Also added a new rpmrs level containing the
latencies and power measurements for this new low power
state.
CRs-Fixed: 369864

Change-Id: I321fa22ab891b929366444f6187876c57f87c421
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: pm: warmboot entry/exit counters on IMEM

Add warmboot entry/exit counters for each core on a non-cacheable always
on IMEM memory. This is a useful feature during debug to understand if
the system has correctly warmbooted after a power collapse. The debug
counters start at a memory offset of 0x664 on the IMEM. Each core
reserves 4 words for events, of which 3 are being used to monitor the
following events,
1) power collapse entry
2) warmboot exit
3) failed power collapse when wfi returns with a pending interrupt.

Change-Id: I45aac8e4a4d3421d586790b3b66fd71a8d88ea9d
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm-8x60: Mark PC counters address as non-cacheable

The power collapse entry counters are incremented after the caches are
flushed during power collapse. In order for the counters to reflect the
current values, in the event of a crash, the counters have to be in a
non-cacheable memory.

Change-Id: If24a41cfa630fe0e843a4d41949ff38e1412889d
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Add power collapse debug counters support.

Add platform device for PC debug counters. These counter stores the
warmboot entry/exit counters for each core on a non-cacheable always
on IMEM memory. This is a useful feature during debug to understand if
the system has correctly warmbooted after a power collapse.

Usage for core0 debug counters:-
counters at address 0x2A03F664 represent no of times PC attempted.
counters at address 0x2A03F66C represent no of times PC failed.
counters at address 0x2A03F668 represent no of times warm boot happened.
no of PC attemps = PC failures + warm boot entries.

Change-Id: I3f78921f1ddd55967284fb7839a98bdb43efbeb9
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: cpufreq: Implement suspend/resume for cpufreq driver

Cpufreq suspend variable get's updated in kernel pm notifier
callback which gets called in process context. This will create
window where cpufreq governor may try to change the frequency
before suspend variable is updated while resume.

Define suspend/resume for cpufreq driver to update suspend variable
in atomic context.

Don't update the policy->cur upon cpufreq driver failure.

CRs-fixed: 423791
Change-Id: Id78705f5c3b8bf801c6253e9362299280903769f
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: kgsl: Add context reference counting to KGSL events

Add reference counting to all KGSL events since they are dependent
on the context.  This avoids a race condition where the context
could be destroyed while the events are being processed during cleanup.

CRs-fixed: 438134
Change-Id: Ic2cd484d441e4c392ab63b0a0131accaceafc711
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Revert "msm_mdp: Add Venus color format support to MDP header file"

This reverts commit 355c0ffe69b90b08ec4621bdb0964b42c6bb7eed.
Reverting it, as this is being handled in Display HAL now.

Change-Id: I2d807a17193c8d579bb23378e59817374d3f4ad7
Signed-off-by: Sushil Chauhan <sushilchauhan@codeaurora.org>
input: sensor: add check if regulator is valid before releasing it

Sensor regulator could be still invalid at the time of a system
suspend, this change is to avoid freeing NULL regulators under such
occasion.

Change-Id: Ia520b2516b43feaa3fbbbe30628cc47ee7fad96a
Signed-off-by: Wentao Xu <wentaox@codeaurora.org>
msm_fb: display: add satge commit without pipes queued

This patch allow satge commit without pipes queued to
allow a pipe to be un-staged from mixer immediately after
overlay_unset.

Change-Id: I03abb907c66cce3d0559743d3bb1eb26a88dc78a
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
msm: vidc: Add the change to prevent memory leak

Memory allocated for "buf_entry" and "sched_cctxt"
is not freed in case if error is returned. This
change prevents possible memory leak in video
decoder driver.

CRs-fixed: 432323
Change-Id: I1c8775fb701f1568f704b6ddbb4e835304d2a817
Signed-off-by: Shobhit Pandey <cshopan@codeaurora.org>
Add full_msm8960-perf_defconfig

* This defconfig is based off msm8960-perf_defconfig
* Enable WLAN in kernel driver configs

Change-Id: Id6beb88349d00e7631344725ff35e9bfd959cf75
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
msm: spm-v2: Add support for AVS

Changing the voltage with the AVS feature enabled requires
certain care. First, temporarily disable AVS before writing any
registers which would change the voltage. Then kick the PMIC
state machine back to the idle state so that our write to the
VCTL register takes effect immediately. We don't need to check
the state machine for idle, instead we should just confirm that
the SPM has sent the voltage we wanted to send and then we can
program AVS to allow up to 4 12.5mV steps down from the voltage
programmed in VCTL. Once this is all done reenable AVS so that
the voltage can be decreased after the AVS_DELAY counts down.

Change-Id: I1c23fd0549e401152fd16de9032ceaf7c3e067c4
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: spm-v2: Disable AVS operations on unsupported targets

Do not enable/disable AVS on targets where it is not enabled at boot.
Enabling it on targets when AVS isn't enabled and the AVS control
parameters aren't configured, causes undefined behavior and random
crashes.

Change-Id: Id0c4e10618437eed1b383145a6a4f25bbd901647
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: spm: enable avs for 8960 hw

Enable avs(bit 27 in SAW2_AVS_CTL) by default
in the board file which can be usefull later to
avoid unneccesarry enable/disables(for avs unsupported
targets).

CRs-fixed: 423827
Change-Id: I2ec49078e2811b8e515260d66462f8ee2ff4e38b
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>